AD652同步V／F转换器的原理与使用

AD652是美国模拟器件公司研制的一种单片、高速、多功能同步V/F转换器。它是AD651的更新产品,管脚排列和功能与AD651完全兼容。一、AD652主要特点和组成 AD652采用电荷平衡技术实现电压频率(V/F)和频率电压(F/V)转换。主要特点有: 1.工作频率高,最高满度频率可达2MHz,由外接时钟确定。转换的准确度决定于外接时钟频率的稳     

频率相位可调的信号源设计

提出了一种直接基于DDS芯片AD9851的信号源的设计方法.介绍了DDS模块的设计,并给出了DDS与FPGA接口电路、DDS信号互补输出电路、DDS七阶低通椭圆滤波电路、DDS信号缓冲放大电路、DDS晶振电路.通过FPGA控制DDS并直接向DDS发送频率控制字,产生常见的正弦波、方波,并实现了频率与相位可调.     

数字频率合成芯片AD9850及其在超声波发射电路中的应用

AD9850是一种高集成度直接数字频率合成器(DDS),该芯片内部集成有高速,高性能D/A转换器和比较器,最高时钟参考频率可达125 MHz.文中详细描述了AD9850的内部结构,功能特点和工作原理,给出了AD9850在超声波发射电路中的具体应用方法.     

AD9854在通信测控系统中的应用

AD9854是Analog Devices公司继AD9850和AD9852之后推出的同一系列的新型直接频率合成器件,具有频率分辨率高、工作频段宽、频率转换速度快及良好的调制特性等优点。根据多年来的工作经验,介绍了AD9854芯片在通信及航天测控领域的多种应用:利用AD9854或结合外围电路产生高稳定度的频率源;在单音模式下灵活运用其软件控制功能产生多种调制信号;在锁频锁相环中用作数控本振等。     

基于 V／F转换器 AD7742的加速度计信号采集电路设计

针对捷联惯导系统对加速度计输出信号需要高精度采集的特点,介绍了采用V/F转换电路对加速度计信号进行采集的优势,并简单介绍了利用FPGA的EDK技术设计内核的过程。由于加速度计输出为模拟电流信号,利用ADC进行采集转换过程容易受温度漂移、参考电压的波动等影响;而I/F电路采集技术虽然精度高但却很难掌握。在这种情况下选用V/F电路对加速度计进行采集处理具有很大优势。介绍了V/F电路硬件设计过程,包括利用V/F转换器AD7742、精密仪表放大器INA118等元器件的使用描述,并利用FPGA对输出频率信号进行采集验证,最后通过试验验证设计的正确性。     

基于CPLD的高分辨率AD转换电路设计

本文从仪器仪表应用领域对温控的需求方面出发,设计了具有高精度、低温漂的16位AD转换电路。模拟输入电压为0-100mV,通过精准的放大和偏置后送给AD652进行V/F变换,转换出来的频率信号由CPLD进行测量,结果送交控制器,产生16位AD转换结果。同时系统可提供0-100mV连续可调的高精度测试用基准源。     

开关电源的缓冲电路设计

随着开关电源工作频率的提高,开关器件承受很大的热量和电应力,从而形成过电压。为此,常常需要设置各种缓冲电路对其进行抑制。重点分析比较了三种缓冲电路,并指出了各自的特点及设计要点。RCD缓冲电路的箝位电压随电阻减小而减小,但损耗增大;LCD缓冲电路的LC谐振频率要求小于开关频率;能量回馈缓冲电路的箝位电压较低,不需要额外的电感。最后,给出了LCD缓冲电路的设计结果,实现了无损耗箝位。     

基于单片机的电压有效值检测系统设计

利用单片机和AD转换器TLC549实现5-50V输入电压的有效值的检测。系统由电压转换电路、AD转换电路、单片机处理电路、显示电路、按键电路和电源电路等组成。文章介绍了对各个电路的设计。系统简单、能实现要求功能,稍微修改一下电路参数值,可实现更高输入电压的转换。     

基于AD9911频率源的设计与实现

设计了一种由单片机PIC18LF4520控制DDS芯片AD9911的频率源电路。阐述了单片机控制DDS的软硬件实现方法,以及AD9911内部寄存器的配置要点。系统设计外围电路简单,可方便地实现对频率源电路输出频率、相位和工作模式的控制,输出信号频率范围为25~75 MHz。实验结果表明,该频率源具有输出频率精确、频率分辨率高和相位噪声低等特点,符合通信系统对频率源的设计要求。     

带输入缓冲电路的12位200兆流水线模数转换器

在12 bit 200 M采样率的模数转换电路(ADC)中实现了片内CMOS输入缓冲电路,输入缓冲电路采用源极跟随器电路构架。通过分析源极跟随器的非线性特点,在输入缓冲电路中加入高通滤波电路、复制电容电路等方式,有效提高了输入缓冲电路的线性度。将该输入缓冲电路用于无数字校准的12 bit 200 M采样率的流水线型模数转换电路(ADC)中,用台积电0.18μm CMOS工艺条件下流片验证,当采样时钟为200 MHz、输入信号频率为10 MHz、振幅为1.4 V_(pp)时其失真噪声比(SNDR)为63.5 dB,无杂散动态范围(SFDR)为78.6 dBc,ADC总体功耗为500 mW。     

150V/200V MOSFET

据《世界电子元器件》2009年9月月刊报道,IR推出一系列150 V和200 VHEXFET功率MOSFET,为开关模式电源(SMPS)、不断电系统(UPS)、反相器和DC马达驱动器等工业应用提供极低的闸电荷(Qg)。随着DC/DC功率转换应用技术的日益进步,开关频率也有所提高,输入电     

800V／10A和1200V／6A绝缘栅双极晶体管的研制

本文简单介绍了８００Ｖ／１０Ａ和１２００Ｖ／Ａ绝缘栅双极晶体管（ＩＧＢＴ）的研制．重点介绍工艺过程和测试结果．     

Ti/Al/Ti/Au and V/Al/V/Au Contacts to Plasma-Etched n-Al0.58Ga0.42N

Cross-sectional transmission electron microscopy was used to study annealed Ti/Al/Ti/Au and V/Al/V/Au ohmic contacts to as-received and plasma-etched n-Al_0.58Ga_0.42N. The reaction depth of low-resistance V-based contacts to as-received n-Al_0.58Ga_0.42N is very limited, unlike previously reported Ti-based contacts to n-Al _x Ga_1−x N. In the present study, the Ti/Al/Ti/Au contacts to as-received n-Al_0.58Ga_0.42N required much higher annealing temperatures than the V-based contacts and also exhibited deeper reactions on the␣order of 40 nm. To achieve a low contact resistance on plasma-etched n-Al_0.58Ga_0.42N, different metal layer thicknesses and processing conditions were required. The Ti- and V-based contacts to plasma-etched n-Al_0.58Ga_0.42N exhibited both similar contact resistances and limited reaction depths, along with the presence of an aluminum nitride layer at the metallization/semiconductor interface. Metal channels penetrate the aluminum nitride layer connecting the top of the metallization to the n-Al_0.58Ga_0.42N. The similarity in phase formation in the contacts to plasma-etched n-Al_0.58Ga_0.42N is likely the reason behind the similarity in specific contact resistances.     

Data dissemination scheduling algorithm for V2R/V2V in multi-channel VANET

Considering that the data dissemination in multi-channel VANET (vehicular ad hoc network),a cooperative data dissemination scheduling algorithm was introduced for V2R(vehicle to roadside unit) and V2V(vehicle to vehicle).The algorithm created initial scheduling operators according to data requisition of vehicles.Then,initial collision graph and collision matrix were generated based on the conflict among initial scheduling operators.After proving the positive semidefinite of collision matrix,SDP (semidefinite programming) was used to channel allocation and collision graph creation.The algorithm then assigned weights for each data requisition according to dwell time and data volume of vehicles in RSU service region.Furthermore,it selected maximum weighted independent set of collision graph.The goal was to satisfy the most urgent data requisitions by V2R/V2V cooperate transmission.Transportation simulation results demonstrate that the proposed solution effectively promotes the service capacity by utilizes the multichannel of VANET and V2R/V2V transmission scheduling.     

汽车用42V/14V转换器模块化技术设计方法

42V～14V汽车双电源结构为电力电子设备的大量使用提供了机会。为了满足这类市场一方面低成本，另一方面严格的温度和体积限制的要求，我们在不同的技术基础上提出了三种设计方法来构件42V／14V DC-DC变换器。这些设计方法都可用于大规模生产，但是都存在一个共同的限制：功率等级受限。因此必须将数个设备并联以达到所需的功率等级。我们进行了实际的设计并对它进行了评估。     

A Monolithically Integrated 12V/5V Switch-Capacitor DC-DC Converter

Motivated by the battery-operated applications that demand compact,lightweight andefficient DC-DC converters,many kinds of converter circuits have been published.Amongthem,resonantconverters and the soft-switching convertershave greatl...     

3V/5V标准单元混合使用的芯片设计

讨论了 0 .9μm标准单元正向设计流程中当电路中存在 5 V和 3 V两种电压时芯片的设计方法 ,包括网表产生与验证 ,版图设计 ,电压转换单元的加入原则。     

A Monolithically Integrated 12V/5V Switch-Capacitor DC-DC Converter

A monolithically integrated 12V/SV switch capacitor DC-DC converter with structure-simplified main circuit and control circuit is presented. Its topological circuit and basic operating principle are discussed in detail. It is shown that elevated operating frequency, increased capacitance and reduced turn-on voltage of the diodes can make the converter's output characteristics improved. Reducing resistance of the equivalent resistors and other parasitic parameters can make the operation frequency higher. As a feasible efficient method to fabricate monolithically integrated converter with high frequency and high output power, several basic circuits are parallelly combined where the serial-parallel capacitance is optimized for the maximum output power. The device selection and its fabrication method are presented. A feasible integration process and its corresponding layout are designed. All active devices including switching transistors and diodes are integrated together with all passive cells including capacitors and resistor on a single chip based on BiMOS process,as has been verified to be correct and practical by simulation and chip test.     

1.5V 3mW CMOS V?I converter with 75 dB SFDR for 6V/sub pp/ input swings

A novel CMOS voltage-to-current converter topology is proposed. The use of nested local feedback loops and the absence of current replication in the signal path provide low sensitivity to transistor mismatch and high linearity. Measurements for a 0.5 mum CMOS prototype show a spurious-free dynamic range (SFDR) of 75 dB for a differential input of 6 V_pp and a dual supply of plusmn1.5 V. The circuit occupies 0.1 mm² and consumes 3 mW     

Compact nA/V triode-MOSFET transconductor

A simple nA/V CMOS transconductor for low-frequency g/sub m/-C filters is presented. To benefit from the lowest g/sub m//I/sub D/ ratio, input transistors operate in the triode region, with g/sub m/ adjusted by their (W/L) and V/sub DS/, the latter a tuning-voltage replica. Since V/sub DS/ surmounts the equivalent noise of the replica circuit, excellent control of g/sub m/ is attained. Simulations support theoretical analysis. A 5Hz bandpass filter was designed, featuring SNR=59.2 dB for THD<1% at 150 mV and 17 nW consumption.