0.18μm CMOS Σ-Δ ADC用数字抽取滤波器设计

采用标准0.18μm CMOS工艺,设计了一种应用于UHF RFIDΣ-Δ模数转换器的数字抽取滤波器,并完成其前后仿真、逻辑综合、布局布线及版图实现等全流程.该滤波器主要实现滤波和降采样功能,由梳状滤波器、补偿滤波器和半带滤波器级联组成.合理选择各级滤波器的结构、阶数并采用规范符号编码(CSD)对其系数进行优化.仿真结果表明:采样频率为64MHz,过采样率为32的二阶Σ-Δ调制器的输出1位码流经过该滤波器滤波后,信噪比达到53.8dB;在1.8V工作电压下,功耗约为15mW.版图尺寸0.45mm×0.45mm,能够满足RFID中模数转换器的要求.     

基于16 bit Sigma-Delta模数转换器的数字滤波器设计

介绍了基于64倍过采样sigma-delta模数转换器的多级抽取滤波器设计.通过采用低功耗的多相分解梳状滤波器结构来代替传统的CIC滤波器结构,使得梳状滤波器部分的功耗降低近5倍.通过对滤波器电路结构的优化,可节省35%的芯片面积占用量.经过仿真及FPGA验证,该滤波器的信噪比达到99 dB,可以实现16位精度模数转换器的设计要求.     

混合滤波器组ADC通路失配偏差的校准方法

 针对各采样通路之间的不匹配影响混合滤波器组ADC的重构精度这一问题,本文提出了一种校准混合滤波器组ADC通路失配偏差的模型,该模型将通路间的增益偏差、相位偏差和带宽失配偏差引入到混合滤波器组ADC中.基于此模型,建立根据输出数据求解超定方程组估算失配偏差的方法,给出引入失配偏差的混合滤波器组的结构,推导出其完美重构条件.设计实现了160MHz 12-bit的两通路混合滤波器组ADC系统,实验结果表明,提出的通路失配偏差的校准方法可提高系统的无杂散动态范围(SFDR)23dB.     

时间交叉模数转换系统的时间失配补偿

时间交叉模数转换结构是提高模数转换系统采样率的一种有效途径。由于制造工艺的局限和布线的差异,这种结构会引入通道失配而限制系统的性能。通道失配包括偏置失配、增益失配和时间失配。文中提出了一种基于快速傅里叶变换（Fast Fourier Transform,FFT）计算时间失配并采用有限冲激响应（Finite Impusle Response,FIR）滤波器对它进行补偿的方法,并通过Matlab仿真验证了算法的有效性和可行性。     

窄带滤波器的设计与DSP实现

基于多抽样率数字信号处理原理,设计窄带FIR滤波器,并在DSP芯片上实现.阐述了实现窄带FIR滤波器的两种特殊的滤波器(积分梳状滤波器和半带滤波器)的原理和设计方法,利用Matlab中的FDATOOL工具箱,能够快速地设计出符合各级性能要求的滤波器,利用Matlab/Simulink中的工具箱,全部采用图形化的编程模式,自动生成DSP源代码.结论为窄带FIR滤波器采用抽样率转换多级实现的方法,有效地降低了滤波器的节数,自动生成的DSP源代码能在DSP芯片上正常运行.     

基于DFT滤波器组的低时延FPGA语音处理实现研究

提出了WOLA（Weighted Overlap-Add）并行结构的低时延DFT滤波器组的设计和FPGA实现方法.为降低系统总体时延,在综合考虑传递失真、混迭失真的基础上,将群时延引入系统目标函数,并采用非对称综合原型滤波器设计方法,提出迭代算法,实现了DFT滤波器组低时延优化设计.通过对DFT滤波器组中分析和综合功能的关键模块采用多路并行乘法、多级流水加法链设计,实现了并行的WOLA结构DFT滤波器组,降低FPGA实现的计算时延.整个设计在Xilinx公司的Zynq7020型号FPGA芯片上进行实现.PESQ测试表明,设计的DFT滤波器组能取得较好的语音质量.与串行WOLA结构的实现对比表明,在16kHz语音采样率下,并行的WOLA结构FPGA实现的总时延能降低1.192ms,其中群时延降低12%,计算时延降低29.2%.     

一种应用于音频的DAC中插值滤波器的设计

设计了一种应用于24位音频DAC中实现128倍过采样的插值滤波器,该插值滤波器采用多级插值的方法,根据前后级采样速率不同的特点,选择不同的滤波器结构.采用一种基于CSD编码的方法来实现一种多相结构,这种多相结构不需要乘法器.该方法在减小了控制系统复杂性的同时也减小了芯片的面积.仿真结果表明,该插值滤波器的通带纹波和阻带衰减都达到了设计要求.     

新型高速CSD编码滤波器及VLSl的实现

通过对BOOTH型乘法器、高速加法器结构和CSD编码滤波器结构的深入研究,开发出一种新型高速CSD编码滤波器结构.采用此结构实现了正交幅度调制器中的一个高速反SINC滤波器,并在ALCATEL 0.35μm CMOS工艺实现.芯片规模7500门,面积1.00mm×0.42mm.     

基于梳状滤波器的FIR数字滤波器设计

根据子滤波器抽头级联法,采用梳状滤波器作为子滤波器,设计了一种新型FIR数字滤波器.通过C语言编程的方法来选择子滤波器阶数,使原型滤波器的过渡带宽度最宽.采用经过变换的通带和阻带边界频率来进行原型滤波器的设计,使得原型滤波器的阶数比传统实现方法低很多.采用该方法实现的FIR滤波器乘法器个数比传统方法少很多,硬件实现更为简单,大幅减小了硬件开销.该方法已成功用于回声消除和噪声抑制芯片,FIR滤波器的面积约为传统方法的50%,用180 nm 3.3 V/1.8 V 6层金属混合信号CMOS工艺流片,结果表明,对于过渡带较窄的滤波器,该方法非常有效.     

基于裸芯片覆膜的薄膜体声波滤波器

该文研制了一种空腔型的薄膜体声波谐振器（FBAR）滤波器裸芯片。利用 FBAR一维 Mason 等效电路模型对谐振器进行设计,然后采用实际制作的谐振器模型形成阶梯型结构FBAR滤波器,利用 ADS 软件对 FBAR滤波器裸芯片进行优化设计。仿真结果表明,FBAR滤波器裸芯片尺寸为1 mm×1 mm×0.4 mm,滤波器的中心频率为3 GHz,中心插损为1.3 dB。采用空腔型结构并制备出FBAR滤波器裸芯片,同时采用覆膜工艺对FBAR裸芯片表面进行覆膜保护,避免裸芯片在使用或运输等过程中被损坏。测试结果显示,覆膜前滤波器裸芯片的中心频率为2.993 GHz,中心插损为1.69 dB;覆膜后滤波器的中心频率为2.997 GHz,中心插损为1.51 dB。对覆膜的影响和覆膜前后的差异进行了分析。     

All-digital background calibration technique for timing mismatch of time-interleaved ADCs

An all-digital background calibration technique for timing mismatch of Time-Interleaved ADCs (TIADCs) is presented. The timing mismatch is estimated by performing the correlation calculation of the outputs of sub-channels in the background, and corrected by an improved fractional delay filter based on Farrow structure. The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time. The proposed technique requires only one filter compared with the bank of adaptive filters which requires (M-1) filters in a M-channel TIADC. In case of a 8 bits four-channel TIADC system, the validity and effectiveness of the calibration algorithm are proved by simulation in MATLAB. The proposed architecture is further implemented and validated on the Altera FPGA board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip, and the synthesized results show that the calibration technique is effective to mitigate the effect of timing mismatch and enhances the dynamic performance of TIADC system.     

一种适用于严重衰减串行链路的3.3 Gbit/s模拟均衡器

介绍了一种用于严重损耗串行链路的连续时间线性均衡器(CTLE)。为了解决传统均衡器存在的过均衡和欠均衡问题,提出了一种低频增益线性可调的改进结构,实现了对不同衰减信道的增益补偿。该结构主要包括均衡滤波模块和直流失调消除模块。均衡滤波模块采用均衡单元串联的结构,提高了对信号高频成分的补偿能力。直流失调消除模块用来消除芯片制造过程中因失配而产生的直流偏移。电路采用TSMC 0.18μm CMOS工艺设计,总面积为1.2 mm×0.65 mm。测试结果表明,当速率为3.3 Gbit/s的数据通过损耗为18.8 dB的信道时,均衡器工作正常。在1.8 V的供电电压下,芯片整体功耗为124.2 mW。     

A low-power digital matched filter for direct-sequencespread-spectrum signal acquisition

This paper presents a low-power 128-tap dual-channel direct-sequence spread-spectrum (DSSS) digital matched-filter chip. Design techniques used to reduce the power consumption of the system include latch-based register file filter structure, a high-rate compression scheme, optimized compressor cells, and semicustom layout design. To further reduce the power consumption and the hardware requirement of the clock tree, a double-edge-triggered clocking scheme is adopted. The proposed chip is fabricated using a 0.8-μm standard CMOS process. As the experimental results of the chip indicate, the matched filter can operate at 50 MHz and dissipates 184 mW at 5-V supply voltage. The supply voltage can be scaled down to 2 V for lower speed applications. As a consequence, the proposed design has low power consumption and can be used for code acquisition of DSSS signals in portable systems     

A Novel Scalable and Storage‐Efficient Architecture for High Speed Exact String Matching

String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware‐based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on‐chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.     

基于ATmega128和CPLD的数字继电保护装置系统设计与实现

介绍了ATmega128单片机与CPLD在数字继电保护保护装置中的硬件设计与应用。单片机与CPLD配合应用,改善了原来传统的由单片机、程序存储器、数据存储器、数据驱动芯片、锁存器、地址译码器等一些外围芯片组成的硬件结构,形成了结构简单而功能全面的CPU＋CPLD结构。大大简化了硬件从而提高了系统的可靠性和抗干扰能力,缩短了开发周期和降低了产品成本。且制造出商用产品,产生了良好的社会和经济效益。     

Low-Area/Power Parallel FIR Digital Filter Implementations

This paper presents a novel approach for implementing area-efficient parallel (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. However, a traditional block filter implementation causes a linear increase in the hardware cost (area) by a factor of L, the block size. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is important to design parallel FIR filter structures that require less area than traditional block FIR filtering structures. In this paper, we propose a method to design parallel FIR filter structures that require a less-than-linear increase in the hardware cost. A novel adjacent coefficient sharing based sub-structure sharing technique is introduced and used to reduce the hardware cost of parallel FIR filters. A novel coefficient quantization technique, referred to as a scalable maximum absolute difference (MAD) quantization process, is introduced and used to produce quantized filters with good spectrum characteristics. By using a combination of fast FIR filtering algorithms, a novel coefficient quantization process and area reduction techniques, we show that parallel FIR filters can be implemented with up to a 45% reduction in hardware compared to traditional parallel FIR filters.     

A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting

The filter bank approach for computing the discrete wavelet transform (DWT), which we call the convolution method, can employ either a nonpolyphase or polyphase structure. This work compares filter banks with an alternative polyphase structure for calculating the DWT-the lifting method. We look at the traditional lifting structure and a recently proposed "flipping" structure for implementing lifting. All filter bank structures are implemented on an Altera field-programmable gate array. The quantization of the coefficients (for implementation in fixed-point hardware) plays a crucial role in the performance of all structures, affecting both image compression quality and hardware metrics. We design several quantization methods and compare the best design for each approach: the nonpolyphase filter bank, the polyphase filter bank, the lifting and flipping structures. The results indicate that for the same image compression performance, the flipping structure gives the smallest and fastest, low-power hardware.     

Application of Adaptive Filtering to Direct-Sequence Spread-Spectrum Code Acquisition

A novel hybrid scheme utilizing an adaptive FIR filter is proposed for acquisition of DS-SS signals. Timing information on the delay offset between the incoming DS-SS signal and the locally generated replica of the spreading code is extracted from the tap-weight vector of the acquisition adaptive filter. Expressions for the mean acquisition time, detection, and false alarm probabilities for a coherent, chip synchronous DS-SS system in AWGN are derived. The improvement in acquisition performance over serial search techniques is twice the length of the adaptive filter. This is similar to that gained by other hybrid schemes that search the same number of cells at a time. However, a significant reduction in hardware complexity is obtained. The proposed system is also compared to a system utilizing a partial matched filter structure. Moreover, the same hardware could be used for code tracking and, hence, eliminating the need for a separate tracking loop.     

基于FPGA的超声波信号处理研究

为了降低超声波流量检测过程中噪声对检测精度的影响,采用FPGA器件构建了FIR滤波器,并提出一种新颖的查表法替代滤波器中的乘法运算。试验结果表明,该滤波器设计方法显著降低了FPGA的片内硬件开销,提高了滤波器的运算速度,并具有良好的降噪效果。     

基于nRF905的无线温度采集系统设计与实现

针对传统温室信息有线采集系统移动性差和难以安装维护的特点,介绍了利用LM35温度传感器,STC公司新一代单片机12LE5630AD和Nordic公司nRF905射频收发器芯片组成的一种多点温度采集系统的设计方案.详细阐述了系统组成结构、工作原理、硬件电路和软件设计.实现了多点温度实时监测.系统硬件构成简练,体积小,功耗...