本征氧化层对Si纳米板弹性模量的影响

采用能量法计算了表面不带氧化层的Si纳米板和表面带不同厚度氧化层的Si纳米板的杨氏模量.结果表明,表面带氧化层的Si纳米板杨氏模量随着板厚度的减小而增加,不带氧化层的则随之降低,但当板厚度增加时,它们都趋于一个定值123GPa.板的杨氏模量随表面氧化层层数的增加而上升,随着板厚度的减小,氧化层的影响起到了决定性的作用.当表面带氧化层的纳米板厚度为50nm时,板的杨氏模量随着氧化层层数的增加从120GPa上升到近200GPa.计算结果解释了目前报道的Si纳米板杨氏模量尺度效应不一致的原因.     

本征氧化层对Si纳米板弹性模量的影响

采用能量法计算了表面不带氧化层的Si纳米板和表面带不同厚度氧化层的Si纳米板的杨氏模量.结果表明,表面带氧化层的Si纳米板杨氏模量随着板厚度的减小而增加,不带氧化层的则随之降低,但当板厚度增加时,它们都趋于一个定值123GPa.板的杨氏模量随表面氧化层层数的增加而上升,随着板厚度的减小,氧化层的影响起到了决定性的作用.当表面带氧化层的纳米板厚度为50nm时,板的杨氏模量随着氧化层层数的增加从120GPa上升到近200GPa.计算结果解释了目前报道的Si纳米板杨氏模量尺度效应不一致的原因.     

单晶硅球表面氧化层测量进展和研究

单晶硅球法是阿伏伽德罗常数量值精密测量以及质量重新定义的一种重要方案。单晶硅球表面的氧化层厚度关系到硅球质量和直径测量结果的修正,并在阿伏伽德罗常数的相对测量不确定度中占到很大比例。讨论了表面层测量中影响椭偏测量的几个基本问题,即单晶硅球不同晶向的光学常数以及表面曲率对椭偏光束的散射效应,评估了对氧化层厚度测量不确定度的影响;对于所采用的间接法的不确定度分量进行了分析。该研究为硅球表面层测量提供了实验和理论依据。     

Si片磨削中砂轮粒径对Si片损伤层的影响

在直径300 mm Si片制备中,利用双面磨削技术能为后续加工提供高精度的表面,但Si片损伤层厚度较大.通过扫描电子显微镜和透射电子显微镜对Si片表面及截面进行观察,得到了经不同粒径的砂轮磨削后的Si片的表面及截面形貌、Si片的表面及亚表面损伤层的厚度并进行了分析比较.结果表明,用粒度更小的3000#砂轮磨削,能够有效地降低Si片表面及亚表面损伤层的厚度,为优化300 mm单晶Si片双面磨削工艺、提高Si片表面磨削质量提供了清晰、量化的实验理论依据.     

晶体Si片切割表面损伤及其对电学性能的影响

对比观察了不同工艺条件下金刚石线锯和砂浆线锯切割晶体Si片的表面微观形貌;分析了其切割机理及去除模式;对比分析了三种不同化学方法钝化Si片的效果和稳定性;采用逐层腐蚀去除Si片的损伤层,使用碘酒对其进行化学钝化,然后测试其少子寿命,分析Si片少子寿命随去除深度的变化趋势,根据Si片少子寿命达到最大值时的腐蚀深度,测试确定Si片的损伤层厚度。经实验测得,砂浆线锯切割Si片的损伤层厚度为10μm左右,金刚石线锯切割Si片的损伤层厚度为6μm左右。结果表明,相比于砂浆线锯切割Si片,金刚石线锯切割Si片造成的表面损伤层更浅,表面的机械损伤也更小。     

热氧化二氧化硅层中氟离子的注入及其分布

本文采用电晕放电技术对硅片的热氧化层注入了氟离子.并通过逐次剥层用椭偏测厚仪测量了剥层后的氧化层厚度,用高频c-v法测量了剥层后的平带电压,从而求得平带电压与氧化层厚度间的关系.并由此求得氧化层中电荷的分布情况.测量结果表明:氟离子注入后,在SiO_2/Si界面处的正电荷面密度比注入前有所增加,在氧化层体内存在有均匀分布的负电荷密度,在靠近SiO_2外表面约100(A|°)左右的区域内,负电荷密度由内向外逐渐增加,在外表面处具有最大的负电荷密度.最后,把我们的结果与Williams的结果进行了比较,并进行了讨论.     

MgO缓冲层对Si衬底上制备Fe3Si薄膜性能的影响

采用磁控溅射方法和热加工工艺在n型Si衬底上溅射不同厚度的MgO层并制备Fe-Si薄膜层,退火后形成Fe3Si/MgO/Si多层膜结构.利用MgO缓冲层对退火时Si衬底扩散原子进行屏蔽,并分析MgO层对Fe3Si薄膜结构和电学性质的影响.通过X射线衍射仪(XRD)、扫描电子显微镜(SEM)和四探针测试仪对Fe3Si薄膜的晶体结构、表面形貌、断面形貌和电阻率进行表征与分析.研究结果表明:当MgO层厚度为20 nm时生成Fe0.9Si0.1薄膜,当厚度为50,100,150和200 nm时都生成了Fe3Si薄膜,生成的Fe3Si和Fe0.9Si0.1薄膜以(110)和(211)取向为主.随MgO缓冲层厚度增加,Si衬底扩散原子对Fe3Si薄膜的影响减小,Fe3 Si薄膜的晶格常数逐渐减小,晶粒大小趋向均匀,平均电阻率呈现先增大后减小趋势.研究结果为后续基于Fe3 Si薄膜的器件设计与制备提供了参考.     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

二次热处理的SrTiO3压敏陶瓷电性能的研究

采用逐层研磨及电测量的方法,对800~1050℃不同温度下,热处理的SrTiO3陶瓷电容–压敏元件的表面氧化层进行了研究。结果表明:该类元件存在明显的表面氧化层结构,且随着热处理温度升高,表面氧化层厚度增大,800~1000℃不同温度热处理的样品,其表面氧化层厚度为26~107μm;表面氧化层内扩散氧的浓度和晶界势垒的高度是由表及里逐渐减小的。     

Si(100)上生长的CoSi_2薄膜的STM研究

在大气中用STM研究了固相反应生长的CoSi2薄膜表面．在Si（100）晶片上用离子束溅射淀积Co／Ti双层膜，经退火处理完成三元固相反应，生成TiN／CoSi2／Si膜，然后经H2SO4和H2O2溶液腐蚀去除TiN膜层得到均匀平整的厚度约为100nm的CoSi2薄膜．AES，XRD等分析表明所得CoSi2膜层是Si（100）衬底的外延生长膜．STM测量结果显示CoSi2薄膜表面结构致密平整，主要由交替出现的平台和台阶结构组成．平台的平均宽度为9nm，台阶高度为2个原子层厚度，分析表明这是由于Si衬底的晶面切割偏离（100）面引起的．平台表面呈平行台阶方向的相距约1．1nm的条状结构．     

Scanning tunneling microscopy investigation of the microtopography of SiO2 and Si surfaces at the Si/SiO2 interface in SIMOX structures

The microtopography of silicon and silicon oxide surfaces in SIMOX structures is investigated by scanning tunneling microscopy. A method of using scanning tunneling microscopy to study Si/SiO₂ interfacial roughness is developed for this purpose. It is shown that the relief of the silicon surface in SIMOX structures is smoother than that of the oxide surface. The observed Si/SiO₂ interfacial roughness is due to oxygen ion implantation in the silicon single crystal. The roughness of the SiO₂ and Si surfaces at the Si/SiO₂ interface is compared for the standard and high-temperature oxidation of the silicon single crystal. Fiz. Tekh. Poluprovodn. 33, 708–711 (June 1999)     

一维纳米硅光子晶体的制备与优化

采用双槽电化学腐蚀法制备了纳米多孔硅,主要研究了腐蚀时间和腐蚀电流对重掺杂p型(100)硅衬底上制备的多孔硅层有效光学厚度的影响,采用U-4100光谱仪、场发射扫描电子显微镜(FESEM)技术对所制备的多孔硅光子晶体的结构和有效光学厚度进行了分析表征。研究结果表明,通过合理地选择腐蚀时间和腐蚀电流,可以比较精确地制备特定有效光学厚度的多孔硅薄膜,此方法可广泛应用于纳米多孔硅光子晶体的制备中。     

X-ray and synchrotron studies of porous silicon

The results of comprehensive studies of layers of porous silicon of different conductivity types, grown by anodizing standard Si(111) substrates in an electrolyte based on fluoric acid and ethanol with the addition of 5% of iodine and kept in air for a long time, are discussed. Measurements are performed by scanning electron microscopy, high-resolution X-ray diffraction, and ultrasoft X-ray spectroscopy using synchrotron radiation. The structural parameters of the layers (thickness, strain, and porosity) and atomic and chemical composition of the porous-silicon surface are determined. It is found that an oxide layer 1.5–2.3-nm thick is formed on the surface of the silicon skeleton. The near-edge fine structure of the Si 2p absorption spectrum of this layer corresponds to the fine structure of the 2p spectrum of well coordinated SiO₂. In this case, the fine structure in the Si 2p-edge absorption region of the silicon skeleton is identical to that of the 2p absorption spectrum of crystalline silicon.     

Thickness estimation of silicon-on-lnsulator by means of the fourier transform of bilinearly transformed infrared reflectance data

Knowledge of film thickness is essential for device design in silicon-on-insulator technology. A new thickness estimation technique, based on the calculation of the spatial frequencies of bilinearly transformed infrared reflectance data in a spectral window, is introduced. The assignment of dominant spectral peaks in the power spectral density curve to the optical thickness of the silicon, silicon dioxide and the combined layer, is also presented. Examples for silicon-on-silicon dioxide with the silicon layer ranging in thickness between 1000 nm and 50 nm, with fixed oxide thickness, are presented. Thickness values of both layers to better than a few percent accuracy, were obtained for silicon layers down to 100 nm and with reduced accuracy for layers as thin as 50 nm.     

The Preparation of Nanocrystalline Silicon by Plasma-Enhanced Hydrogenation for the Fabrication of Light-Emitting Diodes

The fabrication of nanocrystalline silicon light-emitting diodes is reported using a novel plasma-enhanced hydrogenation method. The fabrication process consisted of the deposition of amorphous silicon on a silicon substrate, a hydrogen plasma treatment, and subsequent annealing, and the deposition of TiO₂, indium-tin oxide, and metal contact layers. The entire process was performed at temperatures below 400 degC and is compatible with standard silicon fabrication technologies. The current-voltage (I-V) characteristics of the device showed a rectifying diode behavior where electrons tunneled through the thin TiO₂ layer and recombined with the holes injected from the P-type silicon substrate leading to photon generation. The structure of the nanocrystalline silicon films was investigated by scanning electron and transmission electron microscopies, and the spectral distribution of the emitted light was measured by a cathodoluminescence     

Effective Silicon Oxide Formation on Silica‐on‐Silicon Platforms for Optical Hybrid Integration

This paper describes an effective method for forming silicon oxide on silica‐on‐silicon platforms, which results in excellent characteristics for hybrid integration. Among the many processes involved in fabricating silica‐on‐silicon platforms with planar lightwave circuits (PLCs), the process for forming silicon oxide on an etched silicon substrate is very important for obtaining transparent silica film because it determines the compatibility at the interface between the silicon and the silica film. To investigate the effects of the formation process of the silicon oxide on the characteristics of the silica PLC platform, we compared two silicon oxide formation processes: thermal oxidation and plasma‐enhanced chemical vapor deposition (PECVD). Thermal oxidation in fabricating silica platforms generates defects and a cristobalite crystal phase, which results in deterioration of the optical waveguide characteristics. On the other hand, a silica platform with the silicon oxide layer deposited by PECVD has a transparent planar optical waveguide because the crystal growth of the silica has been suppressed. We confirm that the PECVD method is an effective process for silicon oxide formation for a silica platform with excellent characteristics.     

Study of novel techniques for reducing self-heating effects in SOI power LDMOS

Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.     

Thickness determination for silicon-on-insulator structures

Optical interference at the interfaces of a silicon-on-insulator structure has been used for rapid, nondestructive determination of the silicon and oxide layer thicknesses. The technique is useful for determining the layer thicknesses for wafers in which devices and circuits are subsequently fabricated, especially for very thin silicon films in which the device characteristics depend strongly on the silicon thickness.     

Fabrication of SiGe optical waveguides using VLSI processingtechniques

The fabrication of rib waveguides in SiGe using the local oxidation of silicon (LOCOS) was investigated. Samples consisted of strained Si_.97Ge_.03 or Si_.94Ge_.06 waveguiding layers with silicon cladding layers. The structural stability of these strained layers during thermal cycling up to 1050°C was examined using X-ray rocking curve analysis, scanning electron microscopy, and Nomarski microscopy of etched samples. Since single SiGe layers sufficiently thick to support optical waveguiding are typically above the equilibrium critical thickness, dislocation formation during high-temperature processing is unavoidable. This work concentrated on minimizing these dislocations. It was found that the dislocation density induced by the processing can be minimized by using a strain-compensating mask layer as a barrier to oxidation. For a specified thermal oxide layer thickness, higher oxidation temperatures were found to minimize the dislocation density relative to oxidation at temperatures closer to the metastable limit. Furthermore, the large birefringence found in all strained-layer SiGe waveguides is significantly reduced after LOGOS processing. These effects were used to fabricate the first reported optical waveguides and photonic devices in SiGe using standard VLSI-type processing. The device is a 1.3/1.55-μm duplexer with wavelength isolation of roughly 10 dB     

Effect of epitaxial realignment on the leakage behavior of arsenic-implanted,as-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.