晶圆级封装中的SnPb焊料凸点制作工艺

以晶圆级封装工艺技术(WLP)研究为基础,阐述了电化学淀积SnPb焊料凸点的工艺控制过程。采用电化学淀积方法,制备出150μm高(均匀性为±10μm)的SnPb焊料凸点。经扫描电镜分析,SnPb焊料凸点的成份含量(63/37)控制在5%范围之内。     

2004年IC封装业的技术发展趋向

总部设在新加坡的品圆封装代工公司IPAC表示，在2004年要加强集成电路的晶圆级封装(WLP)的业务，引进先进技术和提供包括晶圆凸点、整合、测试等服务。IPAC将使用先进互连解决方案(AIS)公司拥有的专利技术TCSP制程。TCSP是纯芯片级封装制程的简称，它的封装尺寸等于芯片级尺寸，而且大部分封装制程在晶圆加工阶段完成，使每块芯片的封装成本显著降低。     

封装装配技术所用材料的无铅化

本文简要叙述了无铅化立法确定的最后期限、凸点成形工艺、晶圆片凸点成形电镀技术、凸点下金属化及可靠性问题和无铅化材料的发展方向。从而说明，通过漏印板印刷和电镀的晶圆片凸点形成技术事例，证明可靠的无铅化技术是适合的。     

喷镀系统在凸点制备中的应用

介绍了利用电镀法制造晶圆凸点的典型工艺和喷镀设备.喷镀系统是凸点电镀设备中最关健的部件.通过计算机软件模拟试验,对喷镀系统中的喷杯体和匀流板等各种参数和位置进行了优化设计,并在设备上应用验证.该系统在凸点电镀设备上应用后,在晶圆片上成功做出了高质量的均匀凸点,取得了良好效果.     

蔚华科技推出八大整合解决方案

蔚华科技成立于1987年，总公司设于台湾新竹。为高科技产业最佳整合解决方案领导厂商，提供IC设计、晶圆制造、封装、测试、生产信息系统整合及平面显示器等高科技产业研发、制造，及整合型解决方案。在2007年3月21日举行的Semicon China展会中，针对半导体与FPD产业推出液晶驱动IC测试、SoC设计及IC验证设备、先进封装技术、无线通讯测试、300mm晶圆与平面显示器制造、内存及内存条测试、IC测试配套设备与零组件以及IC验证服务等八大整合解决方案，内容涵盖从IC设计、制造到测试所需的设备与服务，期望持续为客户寻找更完善的解决方案（Seeking Smarter Solutions），提升竞争优势。     

焊球植球凸块工艺的可靠性研究

焊球植球是一种最具潜力的低成本倒装芯片凸块制作工艺.采用焊球植球工艺制作的晶圆级芯片尺寸封装芯片的凸块与芯片表面连接的可靠性问题是此类封装技术研究的重点.为此,参考JEDEC关于电子封装相关标准,建立了检验由焊球植球工艺生产的晶圆级芯片尺寸封装芯片凸块与芯片连接及凸块本身是否可靠的可靠性测试方法与判断标准.由焊球植球工艺生产的晶圆级芯片尺寸封装芯片,分别采用高温存储、热循环和多次回流进行试验,然后利用扫描电子显微镜检查芯片上凸块剖面的凸块下金属层分布和测试凸块推力大小来验证凸块的可靠性.试验数据表明焊球植球工艺生产的晶圆级芯片尺寸封装芯片具有高的封装连接可靠性.     

晶圆芯片级封装(WCSP)面临的发展与挑战

正更多挑战典型WCSP工艺的一个常见问题是缺少最终封装测试。大多数情况下,最终电气测试都是在凸块回流后在晶圆层进行。因此,在制造过程的这一"后端"部分,必须进行高强度的目视检查,其包括激光标记、切割和封装。随着这种封装进入汽车和医疗行业,工艺控制和质量检查系统便成为必需。     

芯片级封装技术研究

对刚性基板倒装式和晶圆再分布式两种结构的芯片级封装（CSP）进行了研究，描述了CSP的工艺流程；详细讨论了CSP的几项主要关键技术：结构设计技术，凸点制作技术，包封技术和测试技术；阐述了采用电镀和丝网漏印制备焊料凸点的方法。     

一种CMOS驱动器的晶圆级芯片尺寸封装

采用晶圆级芯片尺寸封装(WLCSP)工艺完成了一款小型化CMOS驱动器芯片的封装.此WLCSP驱动器由两层聚酰亚胺(PI)层、重分配布线层、下金属层和金属凸点等部分构成.完成了WLCSP驱动器的设计,加工和电性能测试,并且对其进行了温度冲击、振动和剪切力测试等可靠性试验.结果表明,经过晶圆级封装的CMOS驱动器体积为1.8mm×1.2mm×0.35 mm,脉冲上升沿为2.3 ns,下降沿为2.5ns,开关时间为10.6 ns.将WLCSP的驱动器安装至厚度为l mm的FR4基板上,对其进行温度冲击试验及振动试验后,凸点正常无裂痕.无下填充胶时剪切力为20 N,存在下填充胶时,剪切力为200 N.     

圆片级封装的凸点制作技术

圆片级封装是一种先进的电子封装技术,近年来,圆片级封装技术的发展速度很快,主要应用于系统级芯片、光电器件和MEMS等.凸点制作是圆片级封装工艺的关键工序,目前凸点制作工艺方法有多种,重点介绍常用的电镀法、植球法和蒸发沉积法凸点工艺,分别介绍这三种凸点制作技术的工艺流程、关键技术.     

用于圆片级封装的金凸点研制

介绍了电镀法进行圆片级封装中金凸点制作的工艺流程,并对影响凸点成型的主要工艺因素进行了研究.凸点下金属化层(UBM,under bump metallization)溅射、厚胶光刻和厚金电镀是其中的工艺难点,通过大量的实验研究,确定了TiW/Au的UBM体系,得到了优化的厚胶光刻工艺.同时,研制了用于圆片级封装金凸点制作的垂直喷镀设备,选用不同的电镀液体系和光刻胶体系,对电镀参数进行了控制和研究.对制作的金凸点与国外同类产品的基本特性进行了对比,表明其已经达到可应用水平.     

Influence of transient flow and solder bump resistance on underfill process

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60-70 μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.     

电子封装技术发展现状及趋势

现今集成电路晶圆的特征线宽进入微纳电子时代,而电子产品和电子系统的微小型化依赖先进电子封装技术的进步,封装技术已成为半导体行业关注的焦点之一。主要介绍了近年来国内外出现的有市场价值的封装技术,详细描述了一些典型封装的基本结构和组装工艺,并指出了其发展现状及趋势。各种封装方法近年来层出不穷,实现了更高层次的封装集成,因而封装具有更高的密度、更强的功能、更优的性能、更小的体积、更低的功耗、更快的速度、更小的延迟、成本不断降低等优势,其技术研究和生产工艺不可忽视,在今后的一段时间内将拥有巨大的市场潜力与发展空间,推动半导体行业进入后摩尔时代。     

3D芯片封装晶圆植球装备关键技术研究

为了应对半导体芯片高密度、高性能与小体积、小尺寸之间日益严峻的挑战,3D芯片封装技术应运而生.从工艺和装备两个角度诠释了3D封装技术;介绍了国内外3D封装技术的研究现状和国内市场对3D高端封装制造设备植球机的需求.介绍了晶圆植球这一3D封装技术的工艺路线和关键技术,以及研制的这一装备的技术创新点.以晶圆植球机X-Y-θ植球平台为例,分析了选型的技术参数.封装技术的研究和植球机的研发,为我国高端芯片封装制造业的同行提供了从技术理论到实践应用的参考.     

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.     

倒装再分布技术及应用

随着半导体技术的发展,封装工艺与圆片工艺的联系越来越密切,特别是倒装技术的发展及广泛应用。由CSP到WL-CSP,再到TSV技术,封装技术的发展越来越迅速。倒装技术是发展的关键技术,它包括再分布技术、凸点底层金属（UBM）技术、凸点制备技术、倒扣焊接技术和底部填充技术等。文章介绍了传统芯片通过再分布设计及工艺解决实现倒装工艺,为倒装技术以及新技术的开发和应用提供了良好的途径和广阔的空间。     

Electroless nickel/gold bump in the flip-chip-type CMOS package for mobile-phone camera modules

Wafer bumping technology using electroless nickel bump with a thin gold layer was studied for the flip-chip-type CMOS image-sensor (CIS) package for mobile-phone camera modules. The precise control of process parameters in the electroless nickel solution was undertaken by synthetic consideration of the effects of solution temperature, pH, stabilizer concentration, and aluminum pad size on the electroless nickel/gold bump formation. The flip-chip bonding process fitting the electroless nickel/gold bump is conducted by optimization of bonding temperature, pressure, and time. Reliability tests are performed to ensure the robustness of the image-sensor module. The impurity particle density is estimated to be one per 300,000 pixels by 3D laser analysis on the image-sensor surface. The phenomenon of the drop in chip yield during the wet process is attributed to the organic particles produced during the wafer backside coating. From all the experimental results, we first suggest that electroless nickel/gold can be applied to flip-chip-type CIS package for the mobilephone camera module without any significant impurity contamination of the image-sensor surface.     

Hermetic-equivalent packaging of GPS MCM-L modules for highreliability avionics applications

Results are presented of comparative reliability testing of multichip modules (MCM's) fabricated with laminate substrates, and protected with various bare-die coatings. The demonstration MCM's included two design versions (flip-chip and wire-bond) of the digital portion of global positioning system (GPS) receiver multichip modules. This paper summarizes the results for the wire-bonded constructions. Standard encapsulants and new inorganic coatings (Dow Coming's ChipSeal(R) hermetic coating materials') were evaluated in environmental stress exposures corresponding to high reliability avionics applications. Full wafer probe testing was performed both before and after the supplemental ChipSeal processing and dip-chip wafer bump processing steps. ChipSeal and flip-chip wafer processing steps were shown to cause no yield degradation on wafer lots of five different IC types used in the overall program. The environmental test results demonstrate that MCM-L units with bare die packaging can be designed for very robust reliability applications such as military and other high reliability avionics