基于回溯与引导的关键代码区域覆盖的二进制程序测试技术研究

基于路径覆盖的测试方法是软件测试中比较重要的一种测试方法,但程序的路径数量往往呈指数增长,对程序的每一条路径都进行测试覆盖基本上是不可能的。从软件安全测试的观点看,更关心程序中的关键代码区域(调用危险函数的语句、圈复杂度高的函数、循环写内存的代码片断)的执行情况。该文提出了覆盖关键代码区域的测试数据自动生成方法,该方法基于二进制程序,不依赖于源码。通过回溯路径获取所有可达关键代码区域的程序路径,并通过路径引导自动为获得的路径生成相应的测试数据。路径引导策略基于程序的符号执行与实际执行,逐步调整输入,使用约束求解器生成相应的测试用例。理论分析与实验结果显示该文给出的方法可以降低生成测试数据所需要的运行次数,与传统的覆盖路径测试数据生成方法相比,所需要的运行次数显著降低,提高了生成测试数据的效率。     

基于否定选择遗传算法的路径覆盖测试数据生成

路径覆盖是软件测试领域重要的测试方法之一.在搜索空间中,找到一组测试数据满足路径覆盖是一个具有挑战性的问题.因此,自动生成测试数据是软件测试的关键问题.文中提出一种基于否定选择遗传算法的路径覆盖测试数据生成方法,将否定选择策略融入遗传算法,动态优化遗传算法的种群数据,自动生成覆盖目标路径的测试数据.多个基准程序和工业程序的实验结果表明,与随机方法和遗传算法比较,文中方法能够提高路径覆盖率,减少冗余测试数据的生成.     

智能优化算法自动生成软件测试数据的方法探析

软件测试是保证软件质量的有效手段,智能演化算法用于解决软件测试中路径覆盖测试数据的生成问题。本文简要说明了软件测试的类型,分析其中白盒测试的路径覆盖问题、程序插装以及将软件测试数据生成问题转化为优化问题的思想;在随后的智能优化算法部分,介绍了二种智能优化算法,并以其中的遗传算法为例,详细给出了使用遗传算法生成测试数据的步骤,进而说明智能演化算法自动生成测试数据的思想和方法。     

软件测试数据自动生成方法研究

在对软件进行测试中,生成测试用例是一个工作量巨大的工作,若是依靠手工方式生成测试数据则极有可能出现错误.为了保证测试的充分性,测试用例的有效性,本文研究了如何进行测试数据的自动生成,提出了基于遗传算法的软件测试数据的生成方法.本方法利用遗传算法实现测试数据的自动化生成,并在生成的过程中并对测试数据进行测试,解决了路径覆盖的测试.     

基于遗传算法的路径测试用例的自动生成探讨

在软件开发中进行软件测试是为了保证软件质量和可靠性。软件测试中测试数据合理设计很关键。如何优化测试数据,自动生成测试数据是人们一直研究的问题,本文针对测试用例的自动化生成进行了深入的研究,在分析遗传算法的基础上,设计了一个基于遗传算法的测试用例自动生成系统,仿真实践表明,本文设计的系统能够准确地自动生成满足指定路径的测试用例。具有很好的适应性,对程序路径是否被覆盖能智能判断,对不能完全覆盖的程序路径将给出最优解。     

基于CHAM的SA级全路径覆盖方法

文中提出了通过CHAM描述的SA规格说明生成LTS,并根据测试需求进行测试覆盖准则的选取,然后利用全路径测试方法,生成基于此覆盖准则的测试路径.最后以B/ S结构为例,验证了该方法在生成SA级的测试路径上是可行的.     

基于路径自动分割的测试数据生成方法

为了提高路径覆盖测试数据生成效率,研究了路径自动分割方法并结合人工鱼群算法提出了一种路径覆盖测试数据生成方法.首先在分析变量与节点关系、变量与路径关系的基础上提出了路径分割的自动判定及分离算法,实现了变量对子路径有无影响的自动判定;其次引入Levy飞行策略和共轭梯度法对人工鱼群算法进行了改进;然后结合路径分离的结果和改进的人工鱼群算法实现路径覆盖测试数据的生成.在利用人工鱼生成测试数据的过程中,判断是否有人工鱼穿越分离的子路径.如果有,则记录人工鱼中穿越子路径相应的分量并在人工鱼的觅食、聚群及追尾等行为中固定这些分量,从而使得搜索空间不断减少.最后将提出的方法实现程序的测试数据生成,并与相关方法进行了比较.实验结果表明,本文方法在时间开销、成功率及算法稳定性等方面均具有优越性.     

基于遗传算法的UML活动图测试用例优化研究

测试用例的选择在软件测试中十分重要,良好的测试用例可以减少时间和资源的使用,因此提出了一种基于遗传算法的UML活动图自动生成测试用例的算法。通过建立UML活动图模型,将活动图转换为有向图,然后采用深度优先搜索方法获得测试路径,应用遗传算法优化得到测试路径。该算法可以提供优先需要测试的路径,用于自动生成高质量的测试用例,提高测试任务的工作效率。     

基于MC/DC准则的确认测试用例生成方法

形式化的需求规格说明以其能够被自动操纵的形式,精确地描述了软件预期提供的功能,为测试提供了良好的条件。运用模型检查技术自动生成测试用例是形式化方法在基于需求的测试中采用的主要途径。MC/DC(修改的条件/判定覆盖)准则是一种实用的软件结构覆盖率测试准则。结合模型检查技术,提出一种从形式化的软件需求中自动生成测试用例的方法,以达到对软件需求的类似于MC/DC准则的覆盖测试。以一个实际的案例为例,并检验其生成的用例对代码的覆盖率,证明方法的实用性。     

基于数据流的软件测试序列自动生成技术研究

测试用例自动生成技术是软件测试的一个重要研究领域，而如何从待测试程序中选取适当的测试序列集合是其中的一个关键问题。文章提出一种构造结构性测试序列集合的方法，此方法首先对待测试程序进行静态分析，然后根据程序的语句间关系生成程序图，最后基于数据流测试准则，根据程序图以及变量的定义和使用信息构造结构性测试序列集合。在Linux平台上使用这种方法对若干条程序进行分析处理，得到的测试序列集合可以使待测试程序得到充分测试。本文提出的方法具有比较高的测试覆盖，同时，在计算过程中避免了无用路径的生成，节省了算法空间和执行时间。     

基于函数调用的路径覆盖生成技术研究

 针对目前路径覆盖方法所存在的缺陷,提出了一种新的基于函数调用的路径覆盖生成方法.根据控制结构与函数调用语法,获取全部的静态函数调用路径,依据程序执行后的动态路径信息,判断测试用例是否覆盖了程序变更部分及受影响部分.该方法既能避免路径数目的急剧增长,又可以保证测试完全.     

Test Challenges in Nanometer Technologies

Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge.     

基于路径比较的变异测试方法

 提出基于路径比较的变异测试方法.首先,通过比较穿越路径判定变异体是否被杀死;然后,建立基于路径覆盖的变异测试数据生成模型,该模型把杀死变异体作为目标,把满足特定路径覆盖作为约束;最后,采用遗传算法求解该模型.将本文方法应用于典型被测程序,结果表明,该方法可以降低变异测试的难度,并提高测试数据的生成效率.     

LTE系统中自动化测试的设计和实现

作为下一代移动通信系统的标准之一,TD-LTE越来越受到业界和通信厂家的关注。为了对TD-LTE系统的性能做定量指标的测试,需要有较为先进的测试平台和测试方法。为此一个开源的通用测试自动化平台Robot被引入,在此基础上通过开发适用于TD-LTE系统的关键字函数库对TD-LTE系统性能进行测试,并且通过这个测试自动化平台能进行自动的回归测试,不间断地对TD-LTE系统开发中的性能进行测量。通过测试自动化平台提供的日志报告,就能很直观地了解到当前TD-LTE系统的吞吐量性能指标,并对结果进行比较分析。     

COMBINATORIAL DESIGN APPROACHES FOR TEST GENERATION

The n-way combination testing is a specification-based testing criterion, which requires that for a system consisted of a few parameters, every combination of valid values of arbitrary n(n ≥ 2) parameters be covered by at least one test. This letter proposed two different test generation algorithms based on combinatorial design for the n-way coverage criterion. The automatic test generators are implemented and some valuable empirical results are obtained.     

A test methodology for finite state machines using partial scan design

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.This research was sponsored by the Semiconductor Research Corporation, Contract 90-DP-142.     

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.