共查询到19条相似文献,搜索用时 140 毫秒
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通常,计算机与外围设备之间进行数据传送时主要分为并行方式和串行方式两种。并行方式数据吞吐量大,传送速率高,但接口线路复杂,传送距离短。串行接口,工作方式灵活,接口线路简单,传送距离远,但传送速率低是其不足之处。本文旨在介绍一种用DMA 控制的简单实用的高速串行通讯接口,以满足某些方面的通讯需要。 相似文献
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《固体电子学研究与进展》2016,(2)
随着半导体技术的发展,芯片接口的数据传输率制约着芯片性能的提升,采用低压差分接口能够有效提升接口的数据传输率、降低接口功耗并抑制传输噪声。文中介绍了典型的低压差分接口电路及其工作原理,并在此基础上对低压差分接口电路进行了重新设计。设计的低压差分接口电路能够工作在1.8V,数据传输率达1.6Gb/s,功耗0.45mW。 相似文献
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基于FPGA技术的异步双端口RAM设计与实现 总被引:1,自引:0,他引:1
1.引言 在高速数据采集和处理系统中,随着采样数据量的增大及信息处理任务的增加,对数据传送的要求也越来越高.在系统或模块间如果没有能够高速传送数据的接口,则在数据传送时极易造成瓶颈堵塞现象,从而影响整个系统对数据的处理能力.所以,高速并行数据接口的研制在信息处理系统中占有非常重要的地位. 相似文献
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在传统并行同步数字信号的数位和速率将要达到极限的情况下,开始转向从高速串行信号寻找出路,其中以低压差分信号(LVDS)应用最广泛。文中以基于FPGA设计的高速信号下载器为例,从LVDS的PCB设计,约束设置和信号完整性仿真等多方面研究LVDS信号的实现。 相似文献
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当今,从事OC-48、OC-192技术的设计师在设计基于因特网协议(IP协议)的下一代系统时,因系统含有诸如ASIC、网络处理器(NP)、高速跟踪器等元件,以及分组SONET物理层(PoS-PHY)接口规范等的演变,而一直面临挑战。抖动和扭斜失真等现象的存在给诸如系统分组接口第4层(SPI-4)和通用交换接口(CSIX)等总线结构本已拥挤的时序容限,以及四元数据率静态RAM传送表访问时间带来极大混乱。再加上诸如低压差分信号(LVDS)、高速收发逻辑和短线串行终端逻辑等超低电压峰-峰信号技术的引入,使数据出错的可能性变得异常之高。而利用仿真技… 相似文献
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数字通信业务的蓬勃发展对核心元器件的接口带宽提出了越来越高的要求。目前主流元器件解决方案中,主要采用高速串行接口(SerDes)和低压差分接口LVDS实现,但SerDes接口IP价格昂贵。提出一种采用纯数字的采样时钟相位调整和字调整方式,可对源同步数据进行准确采样和恢复,可替代SerDes接口实现10Gb/s16通道LVDS高速接口。本设计方法不依赖于具体的集成电路生产工艺,所使用的IP核是国内主流芯片厂商的主流工艺上都可提供的,可以较低的成本在ASIC芯片上实现高速数据传输接口,满足芯片国产化需求。 相似文献
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Kyeongho Lee Yeshik Shin Sungjoon Kim Deog-Kyoon Jeong Kim G. Kim B. Da Costa V. 《Solid-State Circuits, IEEE Journal of》1998,33(5):816-823
In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electromagnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal-oxide-semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640×480 pixels) up to XGA (1024×768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd 相似文献
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Stievano I.S. Maio I.A. Canavero F.G. Siviero C. 《Advanced Packaging, IEEE Transactions on》2005,28(2):189-196
This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient responses of the modeled devices. The advantages of this macromodeling approach are: improved accuracy with respect to models based on simplified equivalent circuits of devices; improved numerical efficiency with respect to detailed transistor-level models of devices; hiding of the internal structure of devices; straightforward circuit interpretation; or implementations in analog mixed-signal simulators. The proposed methodology is demonstrated on example devices and is applied to the prediction of transient waveforms and eye diagrams of a typical low-voltage differential signaling (LVDS) data link. 相似文献
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介绍了一种基于FPGA的波特率可变、数据位和停止位长度可调、奇偶校验功能可选的RS422串行信号接口电路设计。该设计以Altera的Cyclone系列芯片EP3C80F780I7作为控制芯片,以ADI的ADM2687EBRIZ作为RS422差分信号处理芯片。此外,该设计所有运算功能均采用硬件逻辑实现,具有可靠性高、通用性强的特点。 相似文献
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本文介绍了一种低电磁干扰的用于标准移动图像架构的亚低压差分(subLVDS)接收器,它符合标准移动图像架构(SMIA)标准。由于使用了差分结构和小摆幅信号,它可以同时实现低功耗和高速传输。在本文描述的接收器电路里,高速的共模范围变化的小幅度信号成功的被接收和恢复。本电路在中芯国际1.2V/2.5V1p5m0.13μm CMOS逻辑工艺上投片,伪随机码传输高达1.4Gbps。 相似文献
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Foss R.C. Prince B. Rodgers R. Gustavson D.B. James D.V. Stone G. Kempainen S. 《Spectrum, IEEE》1992,29(10):54-57
The limitations of current nominal 5 V interfaces are examined, and the requirements for interfaces between high-speed DRAMs and processors are outlined. Three solutions are described. One is a center-tap-terminated interface, the second uses Gunning transceiver logic, and the third relies on low-voltage differential signaling 相似文献
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This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively 相似文献
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全谱段光谱成像仪集成可见多光谱、短波/中波红外以及长波红外三种探测器,覆盖十多个谱段,具有目前国内同类遥感仪器最宽光谱信息,同时系统复杂且技术难度较大。为解决全谱段光谱成像仪多探测器同步控制、海量数据存储与集成处理以及探测器在轨增益、级数、积分时间等其他参数调整问题,设计了一种多探测器数据控制与处理系统。该系统硬件以现场可编程门阵列(FPGA)为核心控制处理单元,采用光耦合差分器件与其它设备进行连接和传输;FPGA软件采用模块化设计思想,自顶向下用硬件描述语言(VHDL)进行设计;利用仿真工具、硬件模拟器进行验证,结果证明了该设计的正确性和有效性。在实际工程应用中,该系统功能全面、接口灵活、可靠性高且易扩展。 相似文献