一种矢量编码器的VLSI结构

我们提出了一种基于最小绝对值误差测试（ＭＭＡＥ）矢量编码器的ＶＬＳＩ结构，这一结构采用了误差测度的值不等式判据、预排序的码书和最近邻搜索算法，并采用二分搜索方法和特殊的误差测度计算及比较结构，大大降低了系统的实现规模，同时采用并行流水线等设计技术，可以获得每８个时钟周期编码一个矢量的处理速度。整个系统采用硬件描述语言ＶＨＤＬ和Ｓｙｎｏｐｓｙｓ系统中进行了设计验证和综合。     

硬件描述语言VHDL及其应用

ＶＨＤＬ是一种超高速ＶＬＳＩ硬件描述语言，能对集成电路的功能和结构进行描述，用ＣＡＤ软件将其编译和转换，并自动形成线路，概要地介绍了ＶＨＤＬ的设计组织和数据类型，并对ＶＨＤＬ的特点及其在ＶＬＳＩ设计中的应用要点做了一些探讨。     

VHDL语言的数字系统设计中的应用

在电子设计自动化领域内，用硬件描述语言ＶＨＤＬ和逻辑综合方法是目前最先进的ＣＡＤ手段之一，笔者通过数字大规模集成电路的设计过程介绍ＶＨＤＬ的文件组织，用ＶＨＤＬ对数字系统的分层设计和综合策略。     

VHDL语言在数字系统设计中的应用

在电子设计自动化领域内，用硬件描述语言ＶＨＤＬ和逻辑综合方法是目前最先进的ＣＡＤ手段之一。笔者通过数字大规模集成电路的设计过程介绍ＶＨＤＬ的文件组织、用ＶＨＤＬ对数字系统的分层设计和综合策略。     

在系统可编程技术在硬件设计中的应用

ＩＳＰ（在系统可编程）技术在ＣＭＯＳ ＰＬＤ领域中处于领先地位。ＩＳＰ器件能完成很多的系统性能,所有的器件能够通过一个简单的菊花链结构进行编程,并利用下载电缆将熔丝件写入ＩＳＰ器件。在熟悉ＩＳＰ ＰＬＤ技术的工作原理和ＶＨＤＬ环境并掌握ＩＳＰ开发工具（包括ＷＶＯｆｆｉｃｅ与ｉｓｐＤＳ＋５．０）情况下,利用ＶＨＤＬ将该技术应用到ＭＣＵ硬件的设计,并根据芯片的管脚锁定,利用ＰＲＯＴＥＬ制成一块ＰＣＢ     

用isp—VHDL设计数字系统

运用超大规模可编程器件与电子设计自动化（ＥＤＡ）技术是现代电子技术的发展潮流。用硬件描述语言ＶＨＤＬ设计数字系统、设计综合、仿真均是ＥＤＡ技术的重要内容。文章阐述了用美国Ｌａｔｉｃｅ公司的ｉｓｐＶＨＤＬ软件设计数字系统的方法。     

应用EDA技术设计数字系统

通过数字钟的设计过程,介绍用美国Ａｌｔｅｒａ公司的ＭＡＸ＋ＰＬＵＳⅡ软件设计数字系统的方法和过程,说明了用硬件描述语言ＶＨＤＬ设计数字系统、逻辑综合和仿真等ＥＤＡ技术是数字系统设计的重要手段。     

VDSL技术及发展

作为一种普通双绞铜线上传输速率可达５５Ｍｂｉｔ／ｓ的新技术，ＶＤＳＬ正愈来愈受到人们的普遍关注。本文详细探讨和分析了ＶＤＳＬ技术预计达到的性能、关键技术、以及存在的问题，指出如何ＶＤＳＬ技术与ＡＤＳＬ技术相结合将为建立一个全服务网络提供一个极好的途径。     

掺砷多晶硅特性研究

用ＬＰＣＶＤ方法生长了掺Ａｓ多晶Ｓｉ薄膜，通过能谱分析，扩展电阻测量，扫描电子显微镜观测，发现用ＬＰＣＶＤ方法生长的掺Ａｓ多晶Ｓｉ可获得极高的掺Ａｓ浓度，Ａｓ对衬底材料（ＳｉＯ２或多晶Ｓｉ）具有超常的低温快扩散特性，掺Ａｓ多晶Ｓｉ经高温退火，晶粒大小有反常的变化。利用这些特性可成功地解决ＬＰＣＶＤ法生长掺Ａｓ多晶Ｓｉ所遇到的生长速度愈来愈慢，Ａｓ浓度愈来愈高，难以生长较厚掺Ａｓ多晶Ｓｉ等问题。     

IT图书推荐书目(二)

《ＡＤＳＬ／ＶＤＳＬ原理（翻译版）》 该书是一本系统介绍ＡＤＳＬ／ＶＤＳＬ原理的教材，从ＡＤＳＬ／ＶＤＳＬ的基本原理入手， 对ＡＤＳＬ／ＶＤＳＬ的发展前景、技术特性、运行环境以及ＡＤＳＬ／ＶＤＳＬ在ＷＡＮ中的具体应用作了深入浅出的阐述。第一章介绍了ＡＤＳＬ技术的入门与发展背景；第二章至第五章介绍了ＡＤＳＬ技术的运行环境和基本通信概念，包括双绞线环境、环路分析、功率谱密度和串音模型、串音环境下ＤＳＬ的理论容量；第六章和第七章则分别介绍了ＤＳＬ 技术的调制基础以及ＡＤＳＬ的调制规范；第八章从实用角度介…     

Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters

This paper presents an architecture for quadrature bandpass mismatch shaping that allows the center frequency of the mismatch suppression band to be tunable over the entire Nyquist range. The approach is based on the previously reported complex-valued tree-based mismatch shaper, and extends this to allow tunable operation. The proposed design has been implemented using VHDL and synthesized to logic gates. The hardware complexity and mismatch shaping performance of the proposed architecture are compared to that of a reference architecture, which uses separate tunable mismatch shapers for each complex component path. Simulation results show consistent mismatch shaping performance across the entire tuning range.     

基于IEEE 802．16d OFDM系统的FPGA设计

研究基于IEEE 802．16d OFDM系统的FPGA实现。首先探讨了基于802．16d的OFDM系统FPGA设计的构架。然后采用VHDL硬件描述语言实现了发送端和接收端各个模块。最后选用了Altera公司CycloneⅡ系列的EP2C35F484C6芯片,在QuartusⅡ软件环境下对VHDL代码进行了综合。     

Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos

This article presents an architecture for the fractional motion estimation (FME) of the H.264/AVC video coding standard focusing in a good tradeoff between the hardware cost and the video quality. The support to FME guarantees a high quality in the motion estimation process. The applied algorithmic simplifications together with the multiplierless implementation and with a well balanced pipeline allow a low cost and a high throughput solution. The architecture was also designed to avoid redundant external memory accesses when computing the FME. The design was divided in two main modules: integer motion estimation (with diamond search algorithm) and fractional refinement (half-pixel and quarter-pixel interpolation and search). The designed architecture was described in VHDL and synthesized to an Altera Stratix III FPGA. The architecture is able to reach 260 MHz when running in the target FPGA. In worst case scenario, this operation frequency allows a processing rate of 43 HD 1080p (1,920 × 1,080 pixels) frames per second, surpassing the requirements for real time processing. In comparison to related works, the developed architecture was able to achieve a good tradeoff among hardware costs, video quality and processing rate.     

Flooding-based watershed algorithm and its prototype hardware architecture

Watershed transformation is a powerful image segmentation technique. The potential of its real-time application can be realised by a dedicated hardware architecture. However, little work has been reported so far on hardware realisation of watershed transformation. The authors propose an improved watershed algorithm derived from Meyer's simulated flooding-based algorithm by ordered queues and a prototype FPGA-based architecture for its effective implementation. The improvement in computational complexity results from use of a single queue and conditional neighbourhood comparisons while processing the 3 /spl times/ 3 neighbouring pixels. Besides analysing the computational complexity of the principal steps of the proposed algorithm, the authors present simulation results of running the proposed algorithm and the conventional algorithm on different images for comparison. The proposed architecture has been modelled in VHDL and synthesised for Virtex FPGA. The implementation results show acceptable performance of the proposed architecture.     

H.264帧内预测和模式判断的并行硬件结构设计

针对H.264视频压缩编码算法中帧内预测和模式判断模块,分析并提出了一种高并行度的FPGA实现方法.完成了硬件结构的设计和验证.用VHDL实现本设计,综合后电路最大延迟为8.34 ns.仿真及综合结果表明.该设计能够完全满足高清数字视频的实时处理要求.     

Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC

Block matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18 μm standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5 MHz frequency clock and uses only 28 kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system.     

船载卫通站伺服驱动器告警系统优化方案

优化方案通过以"技防"手段取代"人防",极大地提高了伺服驱动器状态监视的实时性和准确性。结合工程实际分析了信号流程,论证了可行性,合理设计了系统构架,采用EDA技术,以XC95108型复杂可编程逻辑器件(CPLD)为核心硬件电路,辅以外围输入输出设备,在ISE6.0开发环境中运用VHDL硬件描述语言对CPLD进行编程以使其实现设计功能,经过Modulsim平台仿真后载入CPLD芯片。采用以上方式,电路的设计、调试和升级都极为方便。     

基于硬件实现的基因算法的研究

本文提出了一种VLSI实现的硬件基因算法.研究了基因算法的各种变种,探讨了它们的性能及硬件实现的可能性.提出了一个能进行群体存储、父本选择、交叉、变异等操作且易于硬件实现的结构.在硬件实现上,用VHDL描述了整个算法.所作的设计是一个通用的VLSI结构,通过流水线结构和并行化操作获得了很好的性能.硬件实现基因算法有效地缩短运行时间,为实时应用提供了可能.整个设计用Altera公司的FLEX10K40型号的芯片进行了FPGA实现,它完全可以用VLSI来实现.