A 256-Mb multilevel flash memory with 2-MB/s program rate for massstorage applications

A 256-Mb flash memory is fabricated with a 0.25-μm AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm² die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell V_th. The effect of adjacent memory cell's V_th is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell V_th. In the -5-75°C range, memory threshold V_th deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector     

A multipage cell architecture for high-speed programming multilevelNAND flash memories

To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V_th of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 μs/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 33%, and a highly reliable operation can be realized     

A double-level-Vth select gate array architecture formultilevel NAND flash memories

In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, “A double-level-V_th select gate array architecture” to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized     

An automatic temperature compensation of internal sense ground forsubquarter micron DRAM's

This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V _th), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V_th of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V_PP is below 2 V_CC). They are applicable to subquarter micron DRAM's of 256 Mb and more     

Modeling of $V_{rm th}$ Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

A threshold-voltage (V_th) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The V_th shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the V_th shift of NAND flash-memory array and a good agreement with the data from simulation and measurement.     

Threshold voltage uniformity and characterization of microwaveperformance for GaAs/AlGaAs high electron-mobility transistors grown onSi substrates

We report on DC and microwave characteristics for high electron-mobility transistors (HEMT's) grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). Threshold voltage (V _th) distribution in a 3-in wafer shows standard deviation of V_th (σV_th) of 36 mV with V_th of -2.41 V for depletion mode HEMT's/Si and σV_th of 31 mV with V_th of 0.01 V for enhancement mode, respectively. The evaluation of V_th in a 1.95×1.9 mm² area shows high uniformity for as-grown HEMT's/Si with σV_th of 9 mV for V_th of -0.10 V, which is comparable to that for HEMT's/GaAs. Comparing the V_th distribution pattern in the area with that for annealed HEMT's/Si, it is indicated that the high uniformity of V_th is obtained irrelevant of a number of the dislocations existing in the GaAs/Si. From microwave characteristic evaluation for HEMT's with a middle-(10~50 Ω·cm) and a high-(2000~6000 Ω·cm) resistivity Si substrate using a new equivalent circuit model, it is demonstrated that HEMT's/Si have the disadvantage for parasitic capacitances and resistances originated not from the substrate resistivity but from a conductive layer at the Si-GaAs interface. The parasitic parameters, especially the capacitances, can be overcome by the reduction of electrode areas for bonding pads and by the insertion of a dielectric layer under the electrode, which bring high cut-off frequency (f_T) and maximum frequency of operation (f_max) of 24 GHz for a gate length of 0.8 (μm). These results indicate that HEMT's/Si are sufficiently applicable for IC's and discrete devices and have a potential to be substituted for HEMT's/GaAs     

A quick intelligent page-programming architecture and a shieldedbitline sensing method for 3 V-only NAND flash memory

This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-μm NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-μs random access time with a 2.7-V power supply. The page-programming is completed after the 40-μs program and 2.8-μs verify read cycle is iterated 4 times. The block-erasing time is 10 ms     

A 4 Mb NAND EEPROM with tight programmed Vtdistribution

Described is a 5-V-only 4-Mb (512K×8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V_t) distribution, controlled by a novel program-verify technique. A tight programmed V_t distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm×15.31 mm is achieved using 1.0 μm design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance     

一种LTPS-TFT AMOLED像素电路的理论研究

本文对一种LTPS-TFT AMOLED电压型阈值电压(V_(th))补偿像素电路进行了理论研究,分析了影响V_(th)补偿效果的主要因素。电路的补偿效果主要由驱动TFTV_(th)的获取精度和随后的保持精度决定。在V_(th)获取过程中,相关误差主要由驱动TFT转移特性电流对存储电容充电的充电率不足产生;在显示信号与V_(th)叠加过程中,与V_(th)保持节点连接的电容增量等因素会造成V_(th)保持精度的损失。根据分析的结果,本文解释了高分辨率像素电路补偿效果下降的原因。     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

Short-channel-effect free 0.18 μm MOSFET bytemperature-dimension combination scaling theory: design and experiment

We have fabricated 77 K deep-submicron MOSFETs on the basis of the temperature-dimension combination scaling theory (CST). The 77 K MOSFETs with 1-V supply voltage are designed from a 300 K MOSFET with 4-V supply voltage. The fabricated 77 K 0.18 μm device has exhibited fully scaled characteristics. The subthreshold swing (S) and the threshold voltage (V_th) of the 77 K device are found to be 1/4≈77 K/300 K of those of the 300 K device. Furthermore, S and V_th are achieved to be 27 mV/dec and 0.21 V without short-channel effect degradation     

Physically-based threshold voltage determination for MOSFET's ofall gate lengths

A reliable method to determine the threshold voltage V_th for MOSFETs with gate length down to the sub-0.1 μm region is proposed. The method determines V_th by linear extrapolation of the transconductance g_m to zero and is therefore named “GMLE method”. To understand the physical meaning of the method and to prove its reliability for different technologies 2-D simulation was applied. The results reveal that determined V_th values always meet the threshold condition, i.e., the onset of inversion layer buildup     

一种新型a-IGZO TFT集成栅极驱动电路设计

在传统集成栅驱动电路中采用非晶InGaZnO薄膜晶体管(a-IGZO TFT)后会造成信赖性的降低,经过分析确定原因为驱动TFT阈值电压漂移。本文提出了一种改进的集成栅驱动电路,通过对驱动TFT栅节点电压的稳定控制,获得了较大的驱动TFT阈值电压漂移冗余度(从原来的不到±-3V扩大到±-9V),克服了a-IGZO TFT阈值电压漂移所造成的电路失效,稳定了集成栅驱动电路并延长了液晶显示器面板的寿命。     

Threshold voltage model for deep-submicrometer fully depleted SOIMOSFET's

The threshold voltage, V_th, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the V_th roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, ΔV_th is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V _th design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted V_th design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

An efficient back-bias generator with hybrid pumping circuit for1.5-V DRAMs

An efficient back-bias (V_bb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V_bb level of -1.44 V at V_cc=1.5 V, compared to a conventional system in which V_bb only reaches -0.6 V. HPC can pump without the threshold voltage (V_th) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V_bb level lower than -1.0 V is necessary to meet the limitations of the V_th, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection     

Performance and Vdd scaling in deep submicrometer CMOS

Analytical models on metal-oxide-semiconductor field-effect transistor (MOSFET) scaling and complementary (CMOS) ring oscillator performance developed recently are applied to revisit CMOS design guidelines because those based on the basic long channel model are obsolete. Handy and empirical equations for deep submicrometer MOSFET drain saturation current are developed. The differences between the basic long channel model and the accurate deep submicrometer MOSFET current model are highlighted. Design guidelines on V_th and V _dd scaling as well as interconnect loading effects based on the accurate models are presented     

An explicit expression for surface potential at high-end ofmoderate inversion

There is a moderate inversion region between the weak and strong inversion regions of MOSFET operation. This region is very important for designing analog circuits. This paper presents a new explicit expression for the surface potential at the high-end of the moderate inversion, which is useful for a circuit modeling. This expression allows a new definition for the threshold voltage V_th and a model of the relation between off-current I_off and on-current I_on of MOSFETs. A source resistance R_s has large influence on I_on, so that a model for R_s was newly developed. Proposed models for V_th and I_off-I_on characteristics were compared with experiments. It is found that the new definition Of Vth could apply to both short- and long-channel MOSFETs. The model revealed different I_off-I_on behaviors between high and low halo dose MOSFETs     

Robust TFET SRAM cell for ultra-low power IoT applications

Design of ultra-low power SRAM with robust operation for Internet of Thing (IoT) sensor node is a new challenge. In this work, a novel 9T TFET based SRAM bit cell is proposed. The analysis and simulation results demonstrate that the proposed cell eliminates read disturb issue and outperforms the state-of-the-art 9T TFET bit cell in terms of static and dynamic write performance. The presented circuit topology incorporates power cut-off and write ‘0’ only technique to enhance the write performance. The proposed cell exhibits 1.15× higher write margin (WM), 25% lower write delay, consumes 73% (57%) lower write (average) energy, 7% smaller standby leakage power measured at V_DD = 0.3 V. The proposed cell also shows significant improvement in the read/write performance as compared with existing 7T and 8T TFET cells. Our proposed cell also eliminates half-select disturb issue to make it suitable for bit-interleaving architecture that is a must for enhanced soft error immunity.     

Stress-induced leakage current of tunnel oxide derived from flashmemory read-disturb characteristics

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (ΔV_th) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high-temperature (125°C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30°C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures