GCS法及多晶区量子效应的集约建模

提出了一种新的建立集约模型的方法,即栅电容修正法.此方法考虑了新型效应对栅电压的依赖关系,且可以对各种效应相对独立地建模并分别嵌入模型中.另外,利用该方法和密度梯度模型建立了一个多晶区内量子效应的集约模型.该模型与数值模拟结果吻合.模型结果和模拟结果均表明,多晶区内的量子效应不可忽略,且它对器件特性的影响与多晶耗尽效应相反.     

纳米级MOSFET多晶区量子修正解析模型

利用ISE8．0的DESSIS，对多晶区量子力学效应进行了模拟。结果表明，纳米级MOS—FET多晶区内的量子效应不可忽略，且它对器件特性的影响与多晶耗尽效应相反。从密度梯度模型，简化得到多晶区量子效应修正，并建立了多晶区内量子效应的集约模型。该模型与数值模拟结果吻合。     

超薄SiO2栅介质厚度提取与分析

在分析半经典模型和量子模型的基础上,得到包括量子效应和多晶硅耗尽效应的栅氧厚度提取模型.栅介质厚度模拟结果和椭偏仪所测实验结果吻合良好.     

考虑量子效应的MOS器件表面势模型

介绍了目前基于表面势的MOSFET集约模型研究的最新进展,及考虑量子效应时对表面势进行修正的一般方法。并从三角势阱近似出发考虑量子效应,得到了一个新的表面势解析模型,并与经典理论和数值模拟结果进行了比较。模型简单、准确,且物理意义清晰,适合于植入到基于表面势的集约模型中。     

纳米尺度双栅MOS器件反型层电荷的集约建模

建立了双栅MOS器件反型层积分电荷Qi的集约模型.该模型考虑了反型层载流子的量子限制效应,使其适用于纳米尺度的器件应用.基于以前关于Ge的研究,通过建立关于Qi的表面势表达式,可得到一个隐含Qi的方程,从而求得Qi的值.将该模型计算结果与目前已发表的模型计算结果以及自洽求解一维泊松方程和薛定锷方程的数值模拟程序Schred的模拟结果进行了比较.结果表明,该模型在较大的硅层厚度变化范围内均与数值模拟程序的计算结果吻合得很好,显示出其相对与目前发表的其他模型的优越性.     

纳米尺度双栅MOS器件反型层电荷的集约建模

建立了双栅MOS器件反型层积分电荷Qi的集约模型.该模型考虑了反型层载流子的量子限制效应,使其适用于纳米尺度的器件应用.基于以前关于Ge的研究,通过建立关于Qi的表面势表达式,可得到一个隐含Qi的方程,从而求得Qi的值.将该模型计算结果与目前已发表的模型计算结果以及自洽求解一维泊松方程和薛定锷方程的数值模拟程序Schred的模拟结果进行了比较.结果表明,该模型在较大的硅层厚度变化范围内均与数值模拟程序的计算结果吻合得很好,显示出其相对与目前发表的其他模型的优越性.     

超薄SiO_2栅介质厚度提取与分析

在分析半经典模型和量子模型的基础上,得到包括量子效应和多晶硅耗尽效应的栅氧厚度提取模型.栅介质厚度模拟结果和椭偏仪所测实验结果吻合良好.     

小尺寸堆栈高k栅介质GaAs nMOSFET阈值电压模型

通过求解沟道的二维泊松方程,建立了小尺寸高k栅介质GaAs MOSFET的阈值电压模型．模型包括了短沟道效应、漏致势垒降低效应和量子效应．模拟结果与TCAD仿真结果符合较好,证实了模型的正确性和实用性．利用该模型,分析了堆栈高k栅介质结构及其物理参数对阈值电压漂移的影响以及阈值电压的温度特性．结果表明,堆栈栅介质结构能有效抑制边缘场和DIBL效应,改善MOSFET的阈值特性和温度特性;未考虑量子效应的模型过高估计了温度对阈值电压的影响。     

FinFET器件的集约阈电压模型

对FinFET器件(或称三栅MOSFET器件)的二维截面做了解析静电学分析以得出阈电压的计算公式.结果显示,由于三栅结构在高度方向的限制作用,需要引入一个H系数来修正栅电容,随着高度不断变大,它渐近于双栅MOSFET器件的情况.由该解析模型得出的电势分布与数值模拟结果吻合.提出了一个包含量子效应的Fin-FET器件的集约阈电压模型,结果表明,当高度或者顶栅的氧化层厚度变小时,栅电容及阈电压都会上升,这与FinFET设计时发现的趋势是相符合的.     

亚100nm体硅MOSFET集约I-V模型

利用"局域化"的概念和二维泊松方程的解析解,建立了沟道方向上二维量子效应对阈电压的修正模型.基于密度梯度理论,建立了多晶硅栅内量子效应对阈电压的修正模型.在此基础上,结合弹道理论,开发了一个适用于亚100nm MOSFET的集约I-V模型.通过与TSMC提供的沟长为45nm实际器件测试结果[1],以及与三组亚100nm MOSFET的数值模拟结果的比较,证明了该模型具有良好的精度(平均误差小于8%)和可延伸性.     

Two-dimensional quantum effects in nanoscale MOSFETs

In this paper, a full two-dimensional (2-D) quantum mechanical (QM) device simulator for deep submicron MOSFETs is presented. The model couples a 2-D Schrodinger-Poisson solver with a semiclassical transport model. The validity of the proposed model is first tested against a QM model for transport, developed as a benchmark. Then, QM effects on nanoscale MOSFETs performance are quantitatively addressed and discussed. It is shown that QM effects strongly influence the device performance, namely subthreshold slope drain-induced barrier lowering and short-channel effects. These results show that full QM simulations will become a mandatory issue for nanoscale MOSFETs modeling and design     

A new I–V model for surrounding-gate MOSFET considering gate-voltage-dependent quantum effect

We present a new I–V model for a long-channel surrounding-gate (SG) metal–oxide–semiconductor field-effect transistor (MOSFET). SG MOSFET is a strong candidate for next generation nanoscale devices due to a high electrostatic channel control, which in turn substantially reduces the short-channel effect. The new model takes into account quantum mechanical (QM) effects in the SG MOSFET using a double triangular QM well model in the strong inversion regime. In contrast with the old model, we consider the V _g dependence of the QM effect. New model yields excellent agreement with 2-D numerical simulation results for various radii and gate oxide thicknesses of the SG MOSFET.     

Nanoscale electrothermal co-simulation: compact dynamic models of hyperbolic heat transport and self-consistent device Monte Carlo

Two problems in the self-consistent, electrothermal co-simulation of nanoscale devices, are discussed. It is shown that the construction of dynamic compact thermal models for nanoscale devices, based on solution of the hyperbolic (wavelike) heat transport equation, can follow essentially the same approach as the authors' analytical thermal impedance matrix method for the parabolic (diffusive) equation. The physicality of the hyperbolic equation is discussed in the light of calculated results. The analytical impedance matrix method for the time-independent case is employed in a thermally self-consistent device Monte Carlo simulation, illustrating the potential for detailed study of nanoscale electrothermal effects.     

Double Gate MOSFET Modeling Based on Adaptive Neuro‐Fuzzy Inference System for Nanoscale Circuit Simulation

As the conventional silicon metal‐oxide‐semiconductor field‐effect transistor (MOSFET) approaches its scaling limits, quantum mechanical effects are expected to become more and more important. Accurate quantum transport simulators are required to explore the essential device physics as a design aid. However, because of the complexity of the analysis, it has been necessary to simulate the quantum mechanical model with high speed and accuracy. In this paper, the modeling of double gate MOSFET based on an adaptive neuro‐fuzzy inference system (ANFIS) is presented. The ANFIS model reduces the computational time while keeping the accuracy of physics‐based models, like non‐equilibrium Green's function formalism. Finally, we import the ANFIS model into the circuit simulator software as a subcircuit. The results show that the compact model based on ANFIS is an efficient tool for the simulation of nanoscale circuits.     

A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms

The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization.In the present paper,a new approach for modeling semiconductor devices,nanoscale double gate DG MOSFETs,by use of the gradual channel approximation(GC) approach and genetic algorithm optimization technique(GA) is presented.The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction,to achieve reliable,accurate and simple compact models for nanoelectronic circuit simulations.Our compact models give good predictions of the quantum capacitance,threshold voltage shift,quantum inversion charge density and drain current.These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrodinger equations.The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.     

A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET

A backscattering model suitable for compact modeling of nanoscale MOSFET is developed within the Landauer flux-scattering theory. To describe the quasi-ballistic transport, a new backscattering model based on the accurate determination of ballistic and backscattering probabilities along the channel is developed. This model is based on a careful analysis of transport in device using Monte Carlo simulation. This model allows us to display the main physical quantities along the channel and to accurately describe the quasi-ballistic transport and its effects on current-voltage characteristics.     

Analysis of Gain Competition Suppression in Multiwavelength Actively Mode-Locked Erbium-Doped Fiber Lasers Incorporating a Highly Nonlinear Fiber

A numerical model for multiwavelength actively mode-locked erbium-doped fiber lasers (AML-EDFL) is presented. Using the model, the influences of four-wave mixing (FWM) and phase modulation effects (i.e., self-phase modulation (SPM) and cross-phase modulation (XPM)) can be studied, respectively. We use it to investigate AML-EDFLs incorporating a highly nonlinear fiber (HNLF) and explore the mechanisms for gain competition suppression (GCS). The net dispersion of the cavity is found critical for GCS. In the small dispersion regime, FWM dominates GCS, but SPM and XPM deteriorate the output pulses. In the large anomalous dispersion regime, SPM and XPM, however, enhance GCS and produce high-quality pulses. Degree of GCS is also quantitatively evaluated. The simulation results are at last confirmed by experiments.     

Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D integrated circuit (IC) technologies are outlined. A set of physics-based compact models for a multi-scale simulation, to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D through-silicon-via (TSV) technology, is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far.     

A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.