高k栅介质MOSFETs的二维阈值电压模型

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

介绍了一种纳米MOSFET(场效应管)栅电流的统一模型,该模型基于Schrodinger-Poisson方程自洽全量子数值解,特别适用于高k栅介质和多层高k栅介质纳米MOSFET.运用该方法计算了各种结构和材料高k介质的MOSFET栅极电流,并对pMOSFET和nMOSFET高k栅结构进行了分析比较.模拟得出栅极电流与实验结果符合,而得出的优化氮含量有待实验证实.     

高k栅介质纳米MOSFET栅电流模型

介绍了一种纳米MOSFET(场效应管)栅电流的统一模型,该模型基于Schrodinger-Poisson方程自洽全量子数值解,特别适用于高k栅介质和多层高k栅介质纳米MOSFET.运用该方法计算了各种结构和材料高k介质的MOSFET栅极电流,并对pMOSFET和nMOSFET高k栅结构进行了分析比较.模拟得出栅极电流与实验结果符合,而得出的优化氮含量有待实验证实.     

纳米级MOSFET隧穿栅电流量子模型

运用一种全量子模型,研究高k栅介质纳米MOSFET(场效应管)栅电流,特别适用于各种材料高k栅介质和高k叠栅介质纳米MOSFET。使用该方法,研究了高k栅介质中氮含量等元素对栅极电流的影响,并对模拟结果进行了分析比较。结果显示,为了最大限度减少MOS器件的栅泄漏电流,需要优化介质中的氮含量。通过对比表明,模型与实验结果符合。     

高k栅介质MOSFET电特性的模拟分析

对高k栅介质MOSFET栅极漏电进行研究 ,确定栅介质的厚度 ,然后使用PISCES Ⅱ模拟器对高k栅介质MOSFET的阈值电压、亚阈斜率和Idsat/Ioff进行了详细的分析研究。通过对不同k值的MOSFET栅极漏电、阈值电压、亚阈斜率和Idsat/Ioff的综合考虑 ,得出选用k <5 0且Tk/L≤ 0 .2的栅介质能获得优良的小尺寸MOSFET电性能。     

高k栅介质SOILDMOS管阈特性分析与建模

通过分析高k栅介质SOI LDMOS管沟道与埋氧层的关系,建立了SOI LDMOS管的阈特性模型。研究了器件主要结构参数对阈特性及小尺寸效应的影响,分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系。通过软件ISE TCAD进行模拟仿真。结果表明,在不同的tSi和NA条件下,阈值电压的模型计算与数值模拟值吻合率为94.8%,最大差值为0.012 V,不同沟道长度SOI LDMOS的阈值电压漂移率为3.52%,最大漂移电压为0.008 V,模型计算值与数值模拟结果基本吻合。     

深亚微米MOSFET阈值电压模型

文章在分析短沟道效应和漏致势垒降低(DIBL)效应的基础上,通过引入耦合两效应的 相关因子,建立了高k栅介质MOSFET阈值电压的器件物理模型。模拟分析了各种因素对阈值电 压漂移的影响,获得了最佳的k值范围。     

基于氧化铪的高k栅介质纳米MOSFET栅电流模型

运用一种全量子模型研究基于氧化铪的高k栅介质纳米MOSFET栅电流,该方法特别适用于高k栅介质纳米MOS器件,还能用于多层高k栅介质纳米MOS器件。使用该方法研究了基于氧化铪高k介质氮含量等元素对栅极电流的影响。结果显示,为最大限度减少MOS器件的栅电流,需要优化介质中氮含量、铝含量。     

HfO2高k栅介质等效氧化层厚度的提取

分两步提取了HfO2高k栅介质等效氧化层厚度(EOT).首先,根据MIS测试结构等效电路,采用双频C-V特性测试技术对漏电流和衬底电阻的影响进行修正,得出HfO2高k栅介质的准确C-V特性.其次,给出了一种利用平带电容提取高k介质EOT的方法,该方法能克服量子效应所产生的反型层或积累层电容的影响.采用该两步法提取的HfO2高k栅介质EOT与包含量子修正的Poisson方程数值模拟结果对比,误差小于5%,验证了该方法的正确性.     

A comparative study of NEGF and DDMS models in the GAA silicon nanowire transistor

In this article, we have used quantum and semiclassical models to analyse the electrical characteristics of gate all around silicon nanowire transistor (GAA SNWT). A quantum mechanical transport approach based on non-equilibrium Green's function (NEGF) method with the use of mode space approach in the frame work of effective mass theory has been employed for this analysis. Semiclassical drift diffusion mode space (DDMS) approach has also been used for the simulation of GAA SNWT. We have studied the short-channel effects on the performance of GAA SNWT and evaluated the variation of the threshold voltage, the subthreshold slope (SS), the leakage current and the drain-induced barrier lowering (DIBL) when channel length gets shorter. The results showed that quantum mechanical effects increase the threshold voltage and decrease the leakage current, whereas it has also an impact on the SS and DIBL. We have also investigated the effects of high-κ materials as gate dielectric on the device performance.     

后栅工艺高k/金属栅结构NMOSFET偏压温度不稳定性特性研究

本文对后栅工艺高k/金属栅结构NMOSFET偏压温度不稳定性特性进行了研究。在加速应力电压和高温条件下,NMOSFET的阈值电压的退化与时间呈幂指数关系。然而幂指数随应力电压的增大而减小;在本文中,应力从0.6V到12V,幂指数则相应的由0.26减小到0.16。通过对应力前后器件的亚阈值特性分析,在应力过程中没有界面态产生。根据实验数据提取到数值为0.1eV的热激活能,表明偏压温度不稳定性是由栅介质中预先存在的陷阱俘获从衬底隧穿的电子造成的。恢复阶段的测试显示阈值电压的退化与对数时间呈线性关系,同时可以用确定的数学表达式来表明其与应力电压和温度之间的关系。     

一种具有高K栅介质与低k侧壁介质的PNPN型隧穿晶体管研究

本文提出了一种具有高K栅介质及低K侧壁介质的PNPN型隧穿场效应晶体管,并通过二维仿真研究了栅电场和侧壁电场对隧穿场效应晶体管性能的影响。结果表明高K栅介质可以增强栅对沟道的控制能力,同时低K侧墙介质有助于增大带带隧穿的几率。具有这种结构的隧穿场效应晶体管器件具有很好的开关特性、大的开态电流以及良好的工艺容差。该器件可以应用于低功耗领域,并有可能作为下一代CMOS技术的替代者之一。     

A 2D threshold-voltage model for small MOSFET with quantum-mechanical effects

A threshold condition different from the classical one is proposed for MOSFET with quantum effects, and is based on self-consistent numerical solution of the Schrödinger’s and Poisson’s equations. Furthermore, an accurate 1D threshold-voltage model including polysilicon-depletion effects is built by experimental fitting. Simulated results exhibit good agreement with measurement data. Based on this 1D model, a 2D quantum-modified threshold-voltage model for small MOSFET is developed by solving the quasi-2D Poisson’s equation and taking short-channel effects and quantum-mechanical effects into consideration. The model can also be used for deep-submicron MOSFET with high-k gate-dielectric and reasonable design of device parameters.     

Influence of sidewall spacer on threshold voltage of MOSFET with high-k gate dielectric

In this paper, an analytical expression of the gate-dielectric fringing-potential distribution is derived for high-k gate-dielectric MOSFET through a conformal-mapping transformation method for the first time. Based on the fringing-potential distribution, the threshold-voltage model of the MOSFET is improved, and the influence of sidewall spacer on the threshold voltage is discussed in detail. Calculated results indicate that low-k sidewall spacer can alleviate the fringing-field effect.     

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

High-temperature performance of state-of-the-art triple-gate transistors

High-temperature performance of state-of-the-art n-channel triple-gate transistors with 15 nm fin-width, 60 nm fin-height, undoped body, high-k gate dielectric and metal gate is reported. The degradation of the on-current, transconductance and subthreshold swing, the shift in threshold voltage, the increase in gate/drain leakages and off-current with the temperature are analyzed up to 200 °C. The comparison of short- and long-channel devices and the overall excellent performance at high temperature are outlined.     

高K栅介质/金属栅极金属氧化物半导体晶体管平带电压roll-off现象物理起源研究

本文从能带平衡的角度来研究带有高K栅介质/金属栅极的金属氧化物半导体晶体管平带电压roll-off现象,认为随着高K介质与Si衬底之间中间层厚度的减小,高K介质与Si之间直接的电子交换会从无到有,越来越强,而这可能是roll-off现象的起源之一。此外给出了在不同条件下基于此模型得到的理论模拟结果。     

Investigation of the Interfaces in Ni-FUSI/Hf-Based/Si and Ni-FUSI/SiO<Subscript>2</Subscript>/Si Stacks by Physical and Electrical Characterization Techniques

The combination of full Ni silicidation (Ni-FUSI) gate electrodes and hafnium-based high-k gate dielectrics is one of the most promising replacements for poly-Si/SiO₂/Si gate stacks for the future complementary metal–oxide–semiconductor (CMOS) sub-45-nm technology node. The key challenges to successfully adopting the Ni-FUSI/high-k dielectric/Si gate stack for advanced CMOS technology are mostly due to the interfacial properties. The origins of the electrical and physical characteristics of the Ni-FUSI/dielectric oxide interface and dielectric oxide/bulk interface were studied in detail. We found that Ni-FUSI undergoes a phase transformation during silicide formation, which depends more on annealing temperature than on the underlying gate dielectric material. The correlations of Ni–Si phase transformations with their electrical and physical changes were established by sheet resistance measurements, x-ray diffraction (XRD), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) analyses. The leakage current density–voltage (J–V) and capacitance–voltage (C–V) measurement techniques were employed to study the dielectric oxide/Si interface. The effects of the postdeposition annealing (PDA) treatment on the interface charges of dielectric oxides were studied. We found that the PDA can effectively reduce the trapping density and leakage current and eliminate hysteresis in the C–V curves. In addition, the changes in chemical bonding features at HfO₂/Si and HfSiO/Si interfaces due to PDA treatment were evaluated by XPS measurements. XPS analysis provides a better interpretation of the electrical outcomes. As a result, HfSiO films exhibited superior performance in terms of thermal stability and electrical characteristics.