A novel lateral IGBT with a controlled anode for on-off-state loss trade-off improvement

A new lateral insulated-gate bipolar transistor with a controlled anode(CA-LIGBT) on silicon-on-insulator (SOI) substrate is reported.Benefiting from both the enhanced conductivity modulation effect and the high resistance controlled electron extracting path,CA-LIGBT has a faster turn-off speed and lower forward drop, and the trade-off between off-state and on-state losses is better than that of state-of-the-art 3-D NCA-LIGBT,which we presented earlier.As the simulation results show,the ratios of figure of merit(FOM) for CA-LIGBT compared to that of 3-D NCA-LIGBT and conventional LIGBT are 1.45:1 and 59.53:1,respectively.And,the new devices can be created by using additional silicon direct bonding(SDB).So,from the power efficiency point of view,the proposed CA-LIGBT is a promising device for use in power ICs.     

Novel lateral IGBT with n-region controlled anode on SOI substrate

A new lateral insulated-gate bipolar transistor (LIGBT) structure on SOI substrate, called an n-region controlled anode LIGBT (NCA-LIGBT), is proposed and discussed. The n-region controlled anode concept results in fast switch speeds, efficient area usage and effective suppression NDR in forward I-V characteristics. Simulation results of the key parameters (n-region doping concentration, length, thickness and p-base doping concentration) show that the NCA-LIGBT has a good tradeoff between turn-off time and on-state voltage drop. The proposed LIGBT is a novel device for power ICs such as PDP scan driver ICs.     

Three-dimensional pulse-width modulation technique in three-levelpower inverters for three-phase four-wired system

Shunt-connected trilevel power inverter in three-phase four-wired system as an active filter or individual current supply (peak-load supply) is studied by a novel technique: three-dimensional (3-D) voltage vectors pulse width modulation (PWM). In past decades, almost all the study for PWM is limited to the two-dimensional (2-D) domain, α and β frames, in a three-phase three-wired system. However, in practical operation, there are many three-phase four-wired systems in distribution sites. The generalized study of 3-D two-level and three-level inverters is achieved in this paper so as to perform the basic theory of 3-D multilevel space vector switching PWM technique. The sign cubical hysteresis control strategy is proposed and studied with simulation results in 3-D aspect. The 3-D PWM technique in three-level inverters is accomplished     

Three-dimensional modeling from two-dimensional video

This paper presents the surface-based factorization method to recover three-dimensional (3-D) structure, i.e., the 3-D shape and 3-D motion, of a rigid object from a two-dimensional (2-D) video sequence. The main ingredients of our approach are as follows: 1) we describe the unknown shape of the 3-D rigid object by polynomial patches; 2) projections of these patches in the image plane move according to parametric 2-D motion models; 3) we recover the parameters describing the 3-D shape and 3-D motion from the 2-D motion parameters by factorizing a matrix that is rank 1 in a noiseless situation. Our method is simultaneously an extension and a simplification of the original factorization method of Tomasi and Kanade (1992). We track regions where the 2-D motion in the image plane is described by a single set of parameters, avoiding the need to track a large number of pointwise features, in general, a difficult task. Then our method estimates the parameters describing the 3-D structure by factoring a rank 1 matrix, not rank 3 as in Tomasi and Kanade. This allows the use of fast iterative algorithms to compute the 3-D structure that best fits the data. Experimental results with real-life video sequences illustrate the good performance of our approach     

Elevation direction deconvolution in three-dimensional ultrasound imaging

One-dimensional (1-D) linear transducer arrays can be used for three-dimensional (3-D) ultrasound image acquisition. However, the relatively low spatial resolution of these arrays in the elevation direction results in blurry 3-D images. Here, the authors introduce an elevation direction deconvolution (EDD) method that increases the spatial resolution of 3-D ultrasound images in the elevation direction. EDD is based on a deconvolution technique called power spectrum equalization. To evaluate the authors' method, Cartesian volumes were reconstructed with and without EDD from a series of two-dimensional (2-D) images of phantoms. Using these reconstructed volumes, the authors first evaluated the effect of EDD on elevation resolution by computing the full-width-at-quarter-maximum (FWQM) of peaks along lines of constant depth. They then evaluated the effect of EDD on the accuracy of volume calculation by computing the phantom's volumes. EDD decreased the FWQM of the peaks on elevation lines by an average of 17%; however, EDD did not significantly alter the accuracy of volume calculation. It is concluded that EDD can increase the spatial resolution in the elevation direction in 3-D ultrasound images and that EDD may improve the accuracy of volume calculation if a more consistent edge detection method is used.     

Silicon Microrefrigerator

We fabricated a silicon microrefrigerator on a 500-$mu$m-thick substrate with the standard integrated circuit (IC) fabrication process. The cooler achieves a maximum cooling of 1$^circ$C below ambient at room temperature. Simulations show that the cooling power density for a$hbox40times hbox40 muhboxm^2$device exceeds 500$hboxW/cm^2$. The unique three-dimensional (3-D) geometry, current and heat spreading, different from conventional one-dimensional (1-D) thermoelectric device, contribute to this large cooling power density. A 3-D finite element electrothermal model is used to analyze non-ideal factors inside the device and predict its limits. The simulation results show that in the ideal situation, with low contact resistance, bulk silicon with 3-D geometry could cool$sim hbox20 , ^circhboxC$with a cooling power density of 1000$hboxW/cm^2$despite the low thermoelectric figure-of-merit (ZT) of the material. The large cooling power density is due to the geometry dependent heat and current spreading in the device. The non-uniformity of current and Joule heating inside the substrate also contributes to the maximum cooling of silicon microrefrigerator, exceeding 30% limit given in one–dimensional thermoelectric theory$DeltaT_max=hbox0.5hboxZT_c^2$, where$T_c$is the cold side temperature. These devices can be used to remove hot spots on a chip.     

Four-dimensional wavelet compression of arbitrarily sized echocardiographic data

Wavelet-based methods have become most popular for the compression of two-dimensional medical images and sequences. The standard implementations consider data sizes that are powers of two. There is also a large body of literature treating issues such as the choice of the "optimal" wavelets and the performance comparison of competing algorithms. With the advent of telemedicine, there is a strong incentive to extend these techniques to higher dimensional data such as dynamic three-dimensional (3-D) echocardiography [four-dimensional (4-D) datasets]. One of the practical difficulties is that the size of this data is often not a multiple of a power of two, which can lead to increased computational complexity and impaired compression power. Our contribution in this paper is to present a genuine 4-D extension of the well-known zerotree algorithm for arbitrarily sized data. The key component of our method is a one-dimensional wavelet algorithm that can handle arbitrarily sized input signals. The method uses a pair of symmetric/antisymmetric wavelets (10/6) together with some appropriate midpoint symmetry boundary conditions that reduce border artifacts. The zerotree structure is also adapted so that it can accommodate noneven data splitting. We have applied our method to the compression of real 3-D dynamic sequences from clinical cardiac ultrasound examinations. Our new algorithm compares very favorably with other more ad hoc adaptations (image extension and tiling) of the standard powers-of-two methods, in terms of both compression performance and computational cost. It is vastly superior to slice-by-slice wavelet encoding. This was seen not only in numerical image quality parameters but also in expert ratings, where significant improvement using the new approach could be documented. Our validation experiments show that one can safely compress 4-D data sets at ratios of 128:1 without compromising the diagnostic value of the images. We also display some more extreme compression results at ratios of 2000:1 where some key diagnostically relevant key features are preserved.     

Multi-objective module placement for 3-D system-on-package

System-on-package (SOP) is a viable alternative to system-on-chip (SOC) for meeting the rigorous requirements of today's mixed-signal system integration. Thermal integrity is arguably the most crucial issue in three-dimensional (3-D) SOP due to the compact nature of the 3-D integration. In addition, the power supply noise issue becomes more serious as the supply voltage continues to decrease while the number of active devices consuming power increases. We propose a 3-D module and decap (decoupling capacitance) placement algorithm that evenly distributes the thermal profile and reduces the power supply noise. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both maximum temperature and decap amount with only small increase in area, wirelength, and runtime.     

The 3-D Computer

The 3-D Computer [1]–[4] is a unique implementation of a cellular array processor. We have developed two radically new technologies which enable massive numbers of communication channels both between silicon wafers and through them. A parallel processor (single instruction-multiple data stream cellular array processor) has been designed and built to demonstrate the potential of this technological approach. While the 3-D Computer which has been built and operated in a small scale implementation relative to the long-term aims of this technology, it is nevertheless an extremely powerful computer. The current feasibility demonstration 3-D Computer is a 32×32 array of processors partitioned over five wafers stacked one on top of another. The throughput of this current machine is >600 million operations per second (MOPS) with a 10 MHz clock, while the projected throughput of a full scale machine is >100 billion operations per second (BOPS), again with a 10 MHz clock. The extension of the level of circuit integration beyond that of VLSI and WSI, which is made possible by the 3-D technologies of wafer feedthroughs and microbridges, enable us to achieve these enormous throughputs in a very compact form and at very low power. The small size and low power attributes of the 3-D Computer result from the elimination of the chip level and board level packaging and the intraboard wiring required by conventional levels of circuit integration.     

The 3-D Computer

The 3-D Computer [1]–[4] is a unique implementation of a cellular array processor. We have developed two radically new technologies which enable massive numbers of communication channels both between silicon wafers and through them. A parallel processor (single instruction-multiple data stream cellular array processor) has been designed and built to demonstrate the potential of this technological approach. While the 3-D Computer which has been built and operated in a small scale implementation relative to the long-term aims of this technology, it is nevertheless an extremely powerful computer. The current feasibility demonstration 3-D Computer is a 32×32 array of processors partitioned over five wafers stacked one on top of another. The throughput of this current machine is >600 million operations per second (MOPS) with a 10 MHz clock, while the projected throughput of a full scale machine is >100 billion operations per second (BOPS), again with a 10 MHz clock. The extension of the level of circuit integration beyond that of VLSI and WSI, which is made possible by the 3-D technologies of wafer feedthroughs and microbridges, enable us to achieve these enormous throughputs in a very compact form and at very low power. The small size and low power attributes of the 3-D Computer result from the elimination of the chip level and board level packaging and the intraboard wiring required by conventional levels of circuit integration.     

Optimization of PET activation studies based on the SNR measured inthe 3-D Hoffman brain phantom

This work investigates the noise properties of O-15 water positron emission tomography (PET) images in an attempt to increase the sensitivity of activation studies. A method for computing the amount of noise within a region of interest (ROI) from the uncertainty in the raw data was implemented for three-dimensional (3-D) PET. The method was used to study the signal-to-noise ratio (SNR) of regions-of-interest (ROIs) inside a 3-D Hoffman brain phantom. Saturation occurs at an activity concentration of 2.2 mCi/l, which corresponds to a 75-mCi O-15 water injection into a normal person of average weight. This establishes the upper limit for injections for human brain studies using 3-D PET on the Siemens ECAT 921 EXACT scanner. Data from human brain activation studies on four normal volunteers using two-dimensional (2-D) PET were analyzed. The biological variation was found to be 5% 1-ml ROIs. The variance for a complete activation study was calculated, for a variety of protocols, by combining the Poisson noise propagated from the raw data in the phantom experiments with the biological variation. A protocol that is predicted to maximize the SNR in dual-condition activation experiments while remaining below the radiation safety limit is: ten scans with 45 mCi per injection. The data should not be corrected for random or scatter events since they do not help in the identification of activation sites while they do add noise to the image. Due to the lower noise level of 3-D PET, the threshold for detecting a true change in activity concentration is 10%-20% lower than 2-D PET. Because of this, a 3-D activation experiment using the Siemens 921 scanner requires fewer subjects fur equal statistical power     

A generalized Doppler power spectrum for wireless environments

We provide a direct derivation of a generalized Doppler power spectrum of the signal received by a mobile station traveling at a constant velocity. The derivation uses the three-dimensional (3-D) incident radiation intensity and the receiving antenna pattern to obtain an expression for the generalized power spectrum which is useful in environments where the 3-D propagation characteristics of wireless signals must be taken into consideration. A special case of radiation confined to a plane is considered to obtain the power spectrum given in the book written by Jakes (1974)     

Fast splitting alpha-rooting method of image enhancement: tensor representation.

In the tensor representation, a two-dimensional (2-D) image is represented uniquely by a set of one-dimensional (1-D) signals, so-called splitting-signals, that carry the spectral information of the image at frequency-points of specific sets that cover the whole domain of frequencies. The image enhancement is thus reduced to processing splitting-signals and such process requires a modification of only a few spectral components of the image, for each signal. For instance, the alpha-rooting method of image enhancement can be fulfilled through processing separately a maximum of 3N/2 splitting-signals of an image (N x N), where N is a power of two. In this paper, we propose a fast implementation of the a-rooting method by using one splitting-signal of the tensor representation with respect to the discrete Fourier transform (DFT). The implementation is described in the frequency and spatial domains. As a result, the proposed algorithms for image enhancement use two 1-D N-point DFTs instead of two 2-D N x N-point DFTs in the traditional method of alpha-rooting.     

Three-dimensional face reconstruction from a single image by a coupled RBF network

Reconstruction of a 3-D face model from a single 2-D face image is fundamentally important for face recognition and animation because the 3-D face model is invariant to changes of viewpoint, illumination, background clutter, and occlusions. Given a coupled training set that contains pairs of 2-D faces and the corresponding 3-D faces, we train a novel coupled radial basis function network (C-RBF) to recover the 3-D face model from a single 2-D face image. The C-RBF network explores: 1) the intrinsic representations of 3-D face models and those of 2-D face images; 2) mappings between a 3-D face model and its intrinsic representation; and 3) mappings between a 2-D face image and its intrinsic representation. Since a particular face can be reconstructed by its nearest neighbors, we can assume that the linear combination coefficients for a particular 2-D face image reconstruction are identical to those for the corresponding 3-D face model reconstruction. Therefore, we can reconstruct a 3-D face model by using a single 2-D face image based on the C-RBF network. Extensive experimental results on the BU3D database indicate the effectiveness of the proposed C-RBF network for recovering the 3-D face model from a single 2-D face image.     

On the use of 3-D TEM cells for total radiated power measurements

Three-dimensional (3-D) TEM cells offer new issues in EMC immunity and emission testing, where the question of orienting the object under test is no longer raised. This paper starts by presenting the general concept of 3-D TEM cells and hybrid chambers followed by one of the first applications in measuring the total radiated power of devices under test. After a short background on emission measurements in TEM and GTEM cells, the second part of this paper considers a practical industrial case where the total radiated power of an electronic equipment is measured in a 3-D TEM prototype cell, and the results compared to those of TEM and GTEM cells. Finally, the repeatability and reproducibility between TEM, GTEM and 3-D TEM cells is studied and discussed     

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower.     

Colpitts Injection-Locked Frequency Divider Implemented With a 3-D Helical Transformer

This letter proposes a wide locking range and low power complementary Colpitts injection-locked frequency divider (ILFD) employing a 3-D helical transformer. The proposed ILFD consists of two single-ended complementary Colpitts oscillators coupled by a 3-D transformer to form a differential oscillator. The aim of using the 3-D transformer is to reduce chip size. The divide-by-2 LC-tank ILFD is implemented by adding an injection nMOS between the differential outputs of the voltage controlled oscillator. The measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 4.24 to 4.8 GHz. At the incident power of 0 dBm, vtune=0.9 V, and V _DD=1.5 V, the locking range is about 2.4 GHz (26.9%), from the incident frequency 7.7 to 10.1 GHz. The core power consumption is 3.9 mW. The die area is 0.548times 0.656 mm².     

An OFDM with 3-D signal mapper and 2-D IDFT modulator

In this letter, a novel orthogonal frequency division multiplexing (OFDM) is introduced. Here, a three-dimensional (3-D) signal mapper and two-dimensional (2-D) inverse discrete Fourier transform are used to allocate 3-D signals to OFDM subchannels and to modulate the signals, respectively. The minimum Euclidean distance of the 3-D mapper is much farther than that of the 2-D mapper if both mappers consisting of the same number of signal points are normalized to have the same average power. As a result, the proposed OFDM has significantly improved error performance when compared to the conventional one.     

220 GHz折叠波导慢波结构的有损参数化模型

建立了自洽的考虑波导璧损耗的折叠波导等效电路模型,用来计算该慢波结构周期TE10模式中各次空间谐波的相速度,耦合阻抗和线衰减系数.分析结果将会用到220 GHz折叠波导返波管一维束波互作用模型的计算中.当微波频率上升到太赫兹波段时,粗糙波导表面电流导致的壁损将不能再忽略不计.进一步研究表明,起振电流和输出功率水平将和损耗特性的计算密切相关.从原有模型发展而来的有损电路模型可以给出更准确损耗估计.建立了折叠波导慢波线三维谐振腔模型来验证本文的等效电路理论,有较好的吻合.采用了该理论导出参数的一维束波互作用模型和三维数值PIC方法同样有很好的一致性.     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.