Estimated performance of 2.488 Gb/s CPFSK optical non-repeateredtransmission system employing high-output power EDFA boosters

The configuration of a practical nonrepeatered coherent optical transmission system and its performance are reported. The practicability of combining continuous-phase frequency-shift keying (CPFSK) with erbium-doped fiber amplifier (EDFA) boosters is verified by laboratory and field experiments. A system gain of 60.8 dB is achieved at a BER at 10^-11; the EDFA's optical output power is +18 dBm and the receiver sensitivity is -42.8 dBm. The stimulated Brillouin scattering (SBS) effect is examined to estimate the dependence of error rate characteristics on the bit sequence length. No power penalty is observed for a pseudorandom bit sequence (PRBS) of more than 2⁵-1 or STM-16 patterns containing a 30-byte block of consecutive identical digits. The power penalty of 1.3 dB caused by the 310-km non-dispersion-shifted transmission fiber is successfully compensated by installing a chromatic dispersion compensator in each orthogonal polarization branch. During a four month field experiment, error-free operation was observed over a 30 day period, and the long-term error rate is under 6×10^-16     

Optical interconnection using VCSELs and polymeric waveguidecircuits

We investigated the waveguide loss and transmission characteristics for optical interconnection using vertical-cavity surface-emitting lasers (VCSELs) and multimode polymeric waveguide circuits with crossings. The excess loss with 100 crossings is 2.2 dB when the image magnification from a VCSEL to a waveguide is 2.3. We obtained error-free (i.e., bit error rate <10^-11) optical interconnection at 1.0625 Gbps regardless of the number of crossings or the magnification. These results suggest the practicality of large-scale optical interconnection between VCSEL-based smart-pixel chips using multimode waveguides with more than 100 crossings     

An Experimental Validation of a Wavelength-Striped, Packet Switched, Optical Interconnection Network

We experimentally validate a complete optical packet switched interconnection network, implementing the SPINet architecture. The scalable photonic integrated network (SPINet) architecture capitalizes on wavelength division multiplexing (WDM) to provide very large transmission bandwidths, simplify network design, and reduce the network's power dissipation. Contention resolution is performed in the optical domain, and a novel physical layer acknowledgement protocol is employed to mitigate the associated latency and performance penalties. Moreover, the SPINet architecture is specifically designed to enable on-chip integration by not using any kind of optical delay lines. Experiments presented include a complete functionality verification, error-free routing of 80 Gb/s wavelength-striped optical packets (8 wavelengths each modulated at 10 Gb/s) with a bit-error rate (BER) better than 10^-12, and novel performance-enhancement techniques such as path adjustments and load balancing.     

200-Mb/s/ch 100-m optical subsystem interconnections using8-channel 1.3-μm laser diode arrays and single-mode fiber arrays

Synchronous parallel optical-fiber transmission is an attractive method for providing increased interconnection throughput and higher density in advanced information systems. Skew suppression (reducing transmission delay time variation), error-free fully DC-coupled data transmission capability, compactness, and low power consumption of modules are important requirements. In order to meet these requirements, we developed optical subsystem interconnections using long-wavelength laser diode arrays and single-mode fiber arrays. The major design criteria are discussed, especially as they are related to skew due to laser diode turn-on delay and receiver input optical power variation. The use of low-threshold-current laser diode arrays is an important design requirement. Based on the design criteria discussed in this work, we demonstrated and channel 200-Mb/s/ch 100-m transmission using compact (0.18 cc/ch/module), low power (total 280 mW/ch), fully integrated transmitter and receiver modules with an ECL (emitter coupled logic) interface. These modules include our new laser diode arrays with low threshold current of 3.2 mA. Performance results showed that these modules are very effective as interconnections between synchronously operating subsystems     

Performances of lightwave interconnection using spatial addressing(LISA) and its application for multi-processor systems

A novel architecture for free-space optical interconnections is described. Named lightwave interconnections using spatial addressing (LISA), it is comprised of optical array devices and simple electrical logic circuits. One application of LISA, an interconnection bus for multiprocessor systems, is proposed and discussed. The theoretical estimation of LISA's fan-out characteristics concludes that fan-out is limited by the characteristics of signal transmission rather than those of the optical system and the limitation is far higher than imposed by electrical interconnection. A 1×16 LISA was implemented and fundamental operations at 200 Mb/s are demonstrated     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

Optical Interconnection Platform Composed of Fiber-Embedded Board, 90$^{circ}$-Bent Fiber Block, and 10-Gb/s Optical Module

An architecture of a passively assembled optical platform is suggested for a chip-to-chip optical interconnection system. The platform is constructed using all-fiber media for the optical paths: a fiber-embedded optical printed-circuit board (OPCB) and 90-bent fiber connector. The passive assembling was achieved by employing the guide pins/holes of commercialized ferrules in the optical link between the OPCB, 90-bent fiber connector, and the transmitter/receiver (Tx/Rx) module. From this interconnection scheme, a low total optical loss of was obtained. From an assembled platform with 10 Gb/s/ch 4 ch Tx/Rx modules, a 7-Gb/s/ch data transmission was demonstrated with a bit error rate below , involving the optical and electrical crosstalk arisen in the whole channel operation.     

Spectral-Amplitude-Coded OCDMA Optimized for a Realistic FBG Frequency Response

We develop a methodology for numerical optimization of fiber Bragg grating frequency response to maximize the achievable capacity of a spectral-amplitude-coded optical code-division multiple-access (SAC-OCDMA) system. The optimal encoders are realized, and we experimentally demonstrate an incoherent SAC-OCDMA system with seven simultaneous users. We report a bit error rate (BER) of 2.7times10^-8 at 622 Mb/s for a fully loaded network (seven users) using a 9.6-nm optical band. We achieve error-free transmission (BER<1times10^-9) for up to five simultaneous users     

Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

Optical chip-to-chip communication is a promising technology that can mitigate some of the performance short-comings of electrical interconnections, especially bandwidth. Moreover, future high-performance chips are projected to drain hundreds of amperes of supply current. To this end, it is important to develop a high-density and high-performance integrated electrical and optical chip I/O interconnection technology. We describe sea of polymer pillars (or polymer pins), which enables the simultaneous batch fabrication of electrical and optical I/O interconnections at the wafer-level. The electrical and optical I/O interconnections are designed to be laterally compliant to minimize the stresses on the die's low-k dielectric as well as to maintain optical alignment between the coefficient of thermal expansion (CTE)-mismatched board and die during thermal cycling. We demonstrate the fabrication and mechanical performance of various size and aspect ratio electrical and optical polymer pillars. We also describe methods of fabricating polymer pillars with nonflat tip surface area for optical interconnection.     

Realistic end-to-end simulation of the optoelectronic links andcomparison with the electrical interconnections for system-on-chipapplications

A detailed comparison of optoelectronic versus electrical interconnections for system-on-chip applications is performed in terms of signal latency and power consumption. Realistic end-to-end models of both interconnection schemes are employed in order to evaluate critical performance parameters. A variety of electrical and optoelectronic interconnection configurations are implemented and simulated using accurate optical device and electronic circuit models integrated under an integrated circuit (IC) design computer-aided design tool. Two commercial complementary metal-oxide-semiconductor (CMOS) technologies (0.8 μm and 0.25 μm) are used for the estimation of the signal latency and the power consumption as a function of the interconnection length for the different link configurations. It was found that optoelectronic interconnects outperform their electrical counterparts, under certain conditions, especially for relatively long lines and multichannel data links     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks     

2.488 Gb/s-318 km repeaterless transmission using erbium-dopedfiber amplifiers in a direct-detection system

The authors have achieved a 2.488 Gb/s, 318 km repeaterless transmission without any fiber dispersion penalty through a nondispersion-shifted fiber in a direct detection system. The system was loss limited with a T-R power budget of 57 dB. Three key components enabled the authors to achieve this result: (1) a Ti:LiNbO₃ external amplitude modulator enabling a dispersion-free transmission, (2) erbium-doped fiber amplifiers increasing the transmitting power to +16 dBm, and (3) an erbium-doped fiber preamplifier enabling a high-receiver sensitivity of -4.1 dBm for 10^-9 BER. To the author's knowledge, this result is the longest repeaterless transmission span length ever reported for direct detection at this bit rate. From the experimental results and a theoretical model, the authors identified the sources of the receiver sensitivity degradation from the quantum limit (-48.6 dBm) and estimated the practically achievable receiver sensitivity of ~-44 dBm (~-124 photons/bit) for 2.5 Gb/s optical preamplifier detection     

Optimum configuration for cascaded fiber amplifiers in attenuationlimited transmission systems

Fiber amplifiers play an important part in optical transmission systems to overcome the impact of attenuation. Together with the transmitter and receiver the positions of amplifiers on the optical path as well as the design of the amplifiers itself determine the bit error probability of the digital communication link. We present a simple method how to derive the optimum configuration for an optical transmission link with cascaded fiber amplifiers for an attenuation limited system. The bit error probability is calculated in dependence of the positions of the line amplifiers and the lengths of the doped fibers for systems with and without booster and optical preamplifier. In a first step we search the optimum configuration by numerical minimization of the bit error probability for a given transmission length, transmitter power and optical receiver. We have found a very simple rule how to determine the lengths of the transmission fibers and the doped fibers of the amplifiers for the minimum bit error probability when the length of the first transmission fiber is given. Therefore, the search for the optimum configuration reduces to the search of the appropriate length of the first transmission fiber which results in an enormous reduction of computing effort. We have investigated the effect on the bit error probability when one deviates from the optimum configuration. For the case, when the transmission length is reduced me have found that the bit error probability decreases always, when the lengths of the single transmission fibers are cut     

A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs

SRAM-based Field Programmable Gate Arrays (SRAM-FPGA) are more and more employed in today’s applications. In space and avionic applications their operations might be harmed by occurrence of radiation-induced upsets, or Single Event Upsets (SEU), which require the adoption of mitigation techniques. In these devices the majority of the configuration memory rules the interconnection setting. In devices employing “switch matrix” routing, the density of interconnections in switch arrays seems to be a critical point. The higher the interconnection density (i.e., the higher the number of interconnection segments activated by the same switch matrix), the higher the probability of an upset due to a configuration bit controlling the switch matrix. This paper presents an approach to estimate the SEU sensitivity of programmable interconnections of SRAM-based FPGAs as a function of the density of programmable interconnection points inside device configurable logic blocks. A probabilistic model of the SEU effects in programmable interconnection points of Xilinx SRAM-FPGAs is described. The application of the proposed approach to a set of sample designs is illustrated.     

Rules for robust generation of accurate reduced-order models forhigh-speed coupled interconnections

Recently, robust algorithms have been established fur passive order reduction of electrical models of complex interconnection networks. However, very little is known about the way the order of the reduced model should be chosen to ensure accuracy in subsequent transient simulation studies, in this paper, a rule is derived for the selection of the order of the reduced model for interconnections modeled as transmission lines. It is shown that pulse rise time, interconnection length, and physical properties impact the order of the reduced model. The proposed rule is validated through numerical studies involving both analytic and numerical results from the frequency- and time-domain response of multiconductor transmission line circuits     

Multigigabit multichannel optical interconnection module forbroadband switching system

This paper describes optical transmitter and receiver modules for package-to-package interconnection in broadband switching networks such as an asynchronous transfer mode switch fabric. These modules, which include the multiplexer and demultiplexer, can reduce the number of connections and the problem of skew between links. Five-channel optical transmitter and receiver modules were fabricated and demonstrated at 2.8 Gbit/s with a power dissipation of 4.5 W per channel. Moreover, temperature-insensitive optical interconnection was successfully demonstrated by driving a laser with a constant bias current over the threshold and by deducting the optical signal offset. The output power of the transmitter module was -4.2 dBm. Nonuniformity of the transmitter output powers across the range of optical channels was <2.1 dB. Receiver sensitivity for a bit error rate of 10^-11 was -9.3 dBm. Nonuniformity of the receiver sensitivities was <1.5 dB. The power penalty of the receiver sensitivity due to crosstalk was 1 dB. The connection distance was >250 m     

低功耗千兆光互连链路的研制

基于可编程门阵列(FPGA)器件实现了低功耗的高速光互连链路。采用电时分复用(ETDM)技术在1根光纤上实现了G,数据信号的虚拟并行传输,降低了系统成本。链路物理层带宽达1056Mbit／s,链路稳定传输带宽为545Mbit／s,在应用层可得到300Mbit／s的数据传输率。并通过合理的器件选择、动态功耗管理和低功耗编码等设计方法,使系统功耗降低50％。     

20 Gb/s optical soliton data transmission over 70 km usingdistributed fiber amplifiers

20 Gb/s optical soliton data transmission is demonstrated over 70 km. Highly efficient distributed Raman amplifiers for fiber-loss compensation are realized by using high Δn dispersion-shifted single-mode fibers pumped by laser diodes. To achieve high bit rate transmission, optical multiplexing and demultiplexing techniques are also employed. The bit error rate (BER) performance dependence on the input peak power of the optical pulse is measured. No power penalty can be seen at the input peak power required for transmitting optical solitons while the BER performance degrades when decreasing the input peak power     

30 Gb/s Over 100-m MMFs Using 1.1-$mu$ m Range VCSELs and Photodiodes

We developed 1.1-mum-range vertical-cavity surface-emitting lasers based on InGaAs-GaAs quantum wells, back-illuminated InGaAs photodiodes, and transimpedance amplifiers (InP heterojunction bipolar transistor) for high-speed optical interconnection. Clear eye opening operation and error-free transmission at 30 Gb/s over 100-m multimode fibers (GI32) were successfully achieved for the first time.     

40-Gbit/s TDM transmission technologies based on ultra-high-speedICs

This paper presents 40-Gbit/s time division multiplexing (TDM) transmission technologies based on 0.1-μm-gate-length InP high electron mobility transistor IC's and a scheme for upgrading toward a terabit-per-second capacity system. A 40-Gbit/s, 300-km, in-line transmission experiment and a dispersion-tolerant 40-Gbit/s duobinary transmission experiment are described as 40-Gbit/s single carrier system applications on dispersion-shifted fiber. An ultra-high-speed receiver configuration using a high-output-power photodiode is introduced to realize fully electrical receiver operation beyond 40 Gbit/s. The high-sensitivity operation of the optical receiver (-27.6 dBm@BER=10^-9) is demonstrated at a data bit rate of 50 Gbit/s for the first time using a unitraveling carrier photodiode. A dense wavelength division multiplexing (DWDM) system operating up to terabits per second can be easily realized on a zero-dispersion flattened transmission line using ultra-high speed TDM channels of 40 Gbit/s and beyond. An experiment demonstrates 1.04-Tbit/s DWDM transmission based on 40-Gbit/s TDM channels with high optical spectrum density (0.4 bit/s/Hz) without dispersion compensation