Comment: Time-discrete networks

The letter is concerned with time-discrete networks characterised by difference relations. It is shown that a time-discrete network can be defined as an interconnection of lossless transmission lines and multiple parallel transmission lines, resistors and voltage- and current-sequence sources. An approximation of LC components by means of lossless transmission lines is equivalent to the choice of a `trapezoidal? rule of a numerical integration.     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

EMC仿真分析及数值模型设计

阐述了电磁工程设计和测量必须进行建模分析的理念,给出了建立计算机仿真数值模型的方法,包括模板分析方法、电磁源的建模、连接线的建模、系统分析和设计,并通过一个数字信号传输的连接设计示例说明了在数字信号的传输设计中可能遇到的问题。     

A full asynchronous serial transmission converter for network-on-chips

Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power overheads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.     

用于片上网络的全异步串行连接转换器

针对传统片上网络路由器之间互连线过多,传输功耗大的缺陷,提出了一种用于全异步片上网络的串行传输转换器。通过将路由器之间的并行数据分组并以更小的数据块传输,使得片上路由之间的互连线成倍减少,并可以大大减小传输过程带来的功率损耗。零协议逻辑门限门的应用使电路准延时不敏感,提高了转换器的鲁棒性。基于SMIC 0.18μm标准CMOS工艺实现了此串行连接转换器及串行通道。结果表明,在32位数据位宽下,此全异步串行连接转换器可节约路由器之间近3/4的连线资源以及减少近2/3的功耗。此全异步串行连接转换器适用于对面积和功耗较为敏感的片上网络互连应用。     

Analysis and application of a novel model for estimating powerdissipation of optical interconnections as a function of transmissionbit error rate

This paper proposes a novel model for estimating power dissipation of optical/electrical interconnections as a function of transmission bit error rate. This model is applied to a simplified optoelectronic transmitter and receiver configuration in which a photodetector is directly connected to the decision circuit. It is analytically verified that this configuration can achieve error-free operation with low power under practical operating conditions. A comparison between optical and electrical interconnections based on this simplified configuration is performed. This result shows the interconnection length and bit rate at which optical interconnection is superior in terms of power dissipation to electrical interconnection, Only optical interconnections achieve error-free operation with 40 mW power dissipation at a transmission bit rate of 10 Gb/s and an interconnection length over 7 m     

微米级平行互连线的测试结构设计

研究分析无串扰传输理想模型的条件,根据高速高密度电路板中微米级、亚毫米级互连线电磁串扰特性研究需要,首次提出微米级平行互连线的测试结构设计。经射频电路理论分析推导了测试结构对系统串扰没有影响。构建了有、无测试结构的微米级平行互连线物理模型,仿真分析后,加工制作有测试结构的微米级平行互连线电路板。研究结果表明,当数字基带信号传输频率在0~3 GHz 范围时,无测试结构仿真电路模型、有测试结构仿真电路模型、有测试结构的实验电路板,三者串扰特性吻合;微米级平行互连线的测试结构设计合理,具有工程参 考价值。     

A mathematical programming method for constructing the shortest interconnection VLSI arrays

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.     

Selective electroless copper for VLSI interconnection

Cu is studied as a candidate for low-resistance VLSI interconnection. Simulation studies show that for effective channel length less than 0.5 μm, the RC time constant of interconnection is a major part of the total delay. By reducing the resistivity of the interconnect, the operating speed can be increased by more than 20% without any change in design rule. A selective electroless deposition process was used to solve the Cu patterning difficulty. Patterns of 2.2-μm pitch have been achieved with this process. The copper contamination issue is also studied; dielectric films such as silicon oxynitride and silicon nitride are shown to be effective in stopping Cu diffusion. By coating a thin Ni film on Cu, Cu corrosion can be reduced from 0.2 μ/h to less than 0.05 μm/h at 100°C in 4% KCL solution     

发射极空气桥InGaP/GaAs HBT的DC和RF特性分析

为抑制电流增益崩塌,提高HBT的热稳定性,研制了发射极空气桥互连结构的HBT晶体管,应用ICCAP提取参数建立VBIC模型,结合模型参数对三种不同结构HBT的DC和RF特性进行比较分析.与引线爬坡互连结构相比,发射极空气桥互连结构HBT的热阻得到改善,热稳定性提高;与发射极电阻镇流方式相比,发射极空气桥HBT的截止频率(fT)相同,最大振荡频率(fmax)提高,最大稳定功率增益(MSG)高出约5dB.     

Inductance and resistance computations for three-dimensionalmulticonductor interconnection structures

A computer-aided analysis system has been established to calculate the equivalent inductance and resistance matrices for three-dimensional multiconductor interconnection structures. Based on partial element equivalent circuit theory, the interconnection structures are first decomposed into many straight segments which are of circular or rectangular cross sections but can be in arbitrary orientation. The resistances and partial inductances between all these segments are calculated using analytical integration and quadrature formulae. They are assembled into the desired equivalent impedance matrix by general network theory. Illustrative examples include the analysis for nonuniformly coupled transmission lines and the calculation for skin-effect impedances of transmission lines and three-dimensional structures. The numerical results are in good agreement with the measurement data and results in the literature     

A hierarchical clustering network based on a model of olfactory processing

We describe a direct analog implementation of a neural network model of olfactory processing [44–48]. This model has been shown capable of performing hierarchical clustering as a result of a coactivity-based unsupervised learning rule which is modeled after long-term synaptic potentiation. Network function is statistically based and does not require highly precise weights or other components. We present current-mode circuit designs to implement the required functions in CMOS integrated circuitry, and propose the use of floating-gate MOS transistors for modifiable, nonvolatile interconnection weights. Methods for arrangement of these weights into a sparse pseudorandom interconnection matrix, and for parallel implementation of the learning rule, are described. Test results from functional blocks on first silicon are presented. It is estimated that a network with upwards of 50K weights and with submicrosecond settling times could be built with a conventional CMOS double-poly process and die size.     

Libéralisation et charges ďaccès

The paper first reviews some common approaches to setting interconnection charges. It then develops a framework in order to assess these policies and to suggest improvements. The optimal interconnection charges are shown to be discriminatory, and may or may not obey the opportunity cost rule. Their implementation is discussed. Last, the paper shows that, when the number of regulatory targets increases (prevent inefficient bypass of the essential facility, offset users’ market power, etc.), further regulatory instruments are needed if one does not want the interconnection charges to be jack-of-all-trades and masters of none.     

甚短距离光互连模块技术的发展动态

甚短距离光互连技术作为一种突破铜线互连传输瓶颈有效方法,受到了广泛关注。半导体光学器件技术、高速化集成电路技术和光电模块封装技术作为实现光互连的关键技术发展较为迅速。首先阐述了垂直腔面发射激光器的电路模型,然后针对光信号发送模块介绍了预加重补偿技术以及开环方式稳定光功率输出技术,并对如何提高光信号接收模块带宽性能的电路技术进行了分析。其次结合光互连模块技术标准的发展,以NEC公司的实用化甚短距离并行光互连模块为例,对其光电封装技术进行了说明,最后就甚短距离光互连技术所面临的课题及发展前景进行了总结。     

A new discrete transmission line model for passive model orderreduction and macromodeling of high-speed interconnections

A new, computationally efficient, discrete model is presented for passive model order reduction of high-speed interconnections. The proposed discrete model is based on the use of the theory of compact finite differences for the development of the discrete approximation to the transmission line equations that govern wave propagation on the interconnections. Thus result in a discrete model that utilizes only a few unknowns per wavelength and yet provides highly accurate waveform resolution. In addition to improved computational efficiency, the generated discrete model is passive, and compatible with the passive reduced-order interconnect modeling algorithm (PRIMA). Thus, it is suitable for the development of passive reduced-order models of interconnection networks of high complexity. Numerical experiments from the simulation and model order reduction of coupled interconnections are used to illustrate the validity and efficiency of the proposed model     

60GHz 毫米波在芯片无线互连中的传播特性研究

研究了60GHz 毫米波在芯片无线互连特定场景下的电磁传播问题。应用完整电磁理论,以单极阵子为研究对象在收发天线正对、非正对两种情形中,对径向分量在完整电磁波中的作用进行理论分析及数值仿真。数值仿真结果表明:当收发天线间距小于3 倍波长时,径向分量对完整电磁波有一定的贡献;当收发天线间距大于3 倍波长时,可应用传统远场分析进行近似处理。此外,在HFSS 中对特定的芯片间无线互连场景进行了建模及电磁仿真:当天线两端到PCB 介质板的距离约小于0. 7 ~ 0. 8mm 时,PCB 介质板对电磁波的反射会对天线造成一定的频偏,该频偏随着天线到PCB 介质板的距离的增大而减小;当天线两端到PCB 介质板的距离约大于0. 7 ~ 0. 8mm 时,基本不会造成频偏。这为60GHz 毫米波在芯片间无线互连中的应用提供了电磁传播的理论依据。     

基于LTCC的半嵌入式BGA垂直互联结构设计

为满足有源相控阵雷达中发射/接收(T/R)组件的小型轻量化发展要求,提出了一种新型的垂直互联结构。从工艺优化的角度,结合低温共烧陶瓷(LTCC)可制作腔体的特性,用高频结构仿真器HFSS设计了半嵌入式球栅阵列(BGA)垂直互联结构,分析了半嵌入结构对垂直互联传输性能的影响。结果表明半嵌入式BGA垂直互联结构,在X波段回波损耗高于24 dB,插入损耗低于0.15 dB;在Ku波段,依然能实现回波损耗高于20 dB,插入损耗低于0.6 dB。该半嵌入式结构在优化工艺的同时,在X-Ku波段的较宽频段内可实现良好的微波传输性能。     

Stable and Effective Full-Wave PEEC Models by Full-Spectrum Convolution Macromodeling

A novel technique for time domain partial element equivalent circuits (PEECs) modeling is presented. The PEEC method is a well-known numerical method for creating full-wave models of interconnection structures in the frequency and time domains, which are being used for modeling electromagnetic compatibility (EMC) problems. The time domain solutions by PEEC can show the so-called late-time instabilities. Several attempts to overcome this problem have been made in the literature. The cause for instability has been revealed, and a stable time domain model has been given, however, with a reduced computational efficiency. A stable full-wave PEEC model based on a convolution macromodeling with a faster computation time is developed and tested in this paper     

Crosstalk in Balanced Interconnections Used for Differential Signal Transmission

This paper introduces a two-stage model for assessing crosstalk in balanced interconnections used for differential signal transmission, such as multipair cables. The first stage considers the interconnection as uniform and uses a change of variables based on the symmetries inherent to balancing, for the definition of a set of parameters to be measured. The second stage of the model takes into account the nonuniformity related to the fluctuations of the characteristics of the interconnection, using a first order perturbation expansion and a probabilistic approach. This model is compatible with published results on crosstalk in multipair cables.     

Compact packaging of optical and electronic components for on-board optical interconnects

An optical interconnection plate was developed in order to achieve a compact and cost-effective interconnection module for an optical data link between chips on printed circuit boards. On the silica substrate, transmission lines and solder bumps are formed on the top surface of the substrate, and polymer waveguide array with 45/spl deg/ mirror planes is formed on the back side. This optical interconnection plate technique makes the alignment procedure quite simple and economical, because all the alignment steps between the optical components can be achieved in wafer processes and a high accuracy flip-chip bonding technique. We confirmed the sufficiently high coupling efficiency and low optical crosstalk using the simplified experimental setup. Flip-chip bonding of the vertical-cavity surface-emitting laser and photodiode arrays on the top surface of the optical interconnection plate was performed using indium bumps in order to avoid thermal damage of the polymer waveguide. The fully packaged optical interconnection plate showed an optical data link at rates of 455 Mb/s. Improvement of the mirror surface roughness and the mirror angle accuracy could lead to an optical link at higher rates. In addition, the interconnection system can be easily constructed by inserting the optical interconnection plate between the processing chips or data lines requiring optical links.