Two-stage CIC-based decimator with improved characteristics

A simple two-stage multiplierless cascaded-integrator-comb (CIC)-based decimator is presented. The first stage is a cascaded CIC filter whereas the second stage is a cascaded CIC filter and a second-order multiplierless compensator. The proposed decimator can be realised without filtering at high input rate by making use of the polyphase decomposition of the comb filter in the first stage. The proposed filter exhibits high aliasing attenuation and a low passband droop. The design parameters are the decimation factors, M ₁ and M ₂, numbers of cascaded CIC filters L and K, and parameter b of the compensator.     

Novel droop-compensated comb decimation filter with improved alias rejections

This paper presents a novel two-stage comb decimator with the improved magnitude characteristic. Simple multiplierless corrector filters, which are designed using the frequency sampling and IFIR methods, are introduced. The proposed filters compensate the comb passband droop in the wideband passband region and increase the attenuations in the folding bands. Using the multirate identity the filters may be moved to a lower rate. The filter design depends only on the number of the cascaded comb filters and do not depend on the decimation factor M.     

一种基于CIC滤波器的有效锐化方法研究

介绍了对积分梳状滤波器（CIC滤波器）的有效锐化。所提出的锐化滤波器的结构由两个主要部分组成：一个梳状滤波器的级联部分和一个锐化滤波器部分。所提出的方案使得滤波器中锐化部分的工作速率比输入速率大为降低，其频谱响应特性比传统的也有所改进。通过MATLAB仿真，可看出改进锐化后的滤波器性能更优。     

高效数字下变频算法的设计

数字下变频作为一种用于频谱搬移以及降低采样速率的方法,是软件无线电技术的重要组成部分.数字下变频算法主要由抽取滤波器以及FIR滤波器构成.根据下变频频谱变换的特点,首先找到一种符合下变频变换要求的余弦滤波器,根据其存在的不足,通过锐化的方法加以改进.经过分析比较,证明作者所提出的下变频算法是高效可行的.     

A bit-slice architecture for sigma-delta analog-to-digitalconverters

The sigma-delta analog-to-digital converters is based on filtering and undersampling by the digital section of the one-bit output stream coming from the modulation. The structure of this section, consisting of a sine cubic FIR filter decimator followed by an IIR decimator section, is discussed. It is shown that from both signal processing and hardware implementation viewpoints it is advantageous to have the decimation factor of the first stage as large as possible. A bit-slice implementation of the decimation stages is given. It can be easily expanded when higher bit resolutions are required     

Double‐Sharpened Decimation Filter Employing a Pre‐droop Compensator for Multistandard Wireless Applications

This paper presents a double‐sharpened decimation filter based on the application of a Kaiser and Hamming sharpening technique for multistandard wireless systems. The proposed double‐sharpened decimation filter uses a pre‐droop compensator which improves the passband response of a conventional cascaded integrator‐comb filter so that it provides an efficient sharpening performance at half‐speed with comparison to conventional sharpened filters. In this paper, the passband droop characteristics with compensation provides –1.6 dB for 1.25 MHz, –1.4 dB for 2.5 MHz, –1.3 dB for 5 MHz, and –1.0 dB for 10 MHz bandwidths, respectively. These results demonstrate that the proposed double‐sharpened decimation filter is suitable for multistandard wireless applications.     

A Comparison Design of Comb Decimators for Sigma-Delta Analog-to-Digital Converters

This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.     

应用于ΣΔADC的多级抽取滤波器面积有效实现方法

本文介绍了一种用于音频过采样模数转换器的多级抽取滤波器的面积有效实现方法。抽取滤波器的抽取倍数为256,通带波纹小于0.005dB,阻带抑制达到100dB。通带范围为0-20kHz,输出为48kHz的16比特信号。通过采用含RAM和ROM的面积有效架构,以及对一个运算周期中有效的指令调度,该抽取滤波器在XilinxFPGA上综合后仅使用了不到300个LUT和不到160个Slice。不同于串行或部分串行架构中运算速率通常大于输入采样速率的情况,该实现方法可使得运算速率和采样速率一致,从而简化整体ΣΔADC设计并降低功耗。架构中RAM和ROM的采用使得该抽取滤波器可编程,进一步可改进用于自适应滤波应用。最后,在Modelsim中的RTL仿真结果通过Matlab\Simulink程序进行了验证。     

A stereo audio sigma-delta A/D-converter

A stereo sigma delta A/D-converter for audio applications is presented. In this converter, two identical cascaded fourth-order sigma-delta modulators and a sophisticated multistage linear-phase FIR decimation filter with oversampling ratio of 64 are implemented on the same die. The analog part is designed to operate at a low voltage with a low power consumption. Techniques to achieve simultaneously a high performance and a low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than 120 dB and the passband ripple of the overall converter is less than 0.0003 dB. The first decimation stage is a special tapped comb filter, whereas the remaining stages are realized without general multipliers by simultaneously implementing all the filter coefficients by using special bit-serial networks. For the integrated overall stereo converter, the power consumption and the signal-to-noise ratio are 180 mW and 97 dB (85 mW and 95 dB) for a 5 V (3 V) power supply. The circuit die area is only 4.7 mm×5.5 mm using a 1.2 μm double-poly BiCMOS process     

Optimum FIR and IIR multistage multirate filter design

A theorem is introduced which is useful in deriving equivalent multirate filter structures. Frequency responses of multistage multirate filters are derived and defined by deriving their equivalent one-stage filters. A design principle is proposed to reduce filtering requirements at each stage and move the filter operations to low-sampling-rate stages and thus result in a lower arithmetic rate. Optimum FIR and IIR multistage multirate filter designs are developed based on this principle. The new design has a one-point passband specification for each decimator and/or interpolator stage resulting in a wider transition region and lower filter order. Examples are given to explain the design procedure, and comparisons are made to show the superiority of the new filters.     

一种采用斩波稳零技术的16位,96kHz带宽Σ-Δ AD转换器

介绍了一个16位精度Σ-Δ型模拟数字转换器.它由一个模拟的调制器和一个数字降采样滤波器组成.调制器采用了传统的单环两阶的结构,在第一阶调制器中采用了斩波稳零技术来消除电路的闪烁噪声.数字的降采样器包括多相梳状滤波器和波数字滤波器,功耗低,面积小.实验结果表明转换器获得了92dB的动态范围和96kHz的带宽.整个芯片由0.18μm六层金属CMOS工艺制造,芯片面积为2.68mm2,功率消耗仅为15.5mW.     

Representations of Linear Dual-Rate System Via Single SISO LTI Filter, Conventional Sampler and Block Sampler

In this brief, it is proved that a linear dual-rate system can be represented via a series cascade of: 1) a conventional expander, a single-input single-output (SISO) linear time-invariant (LTI) filter and a block decimator, or 2) a block expander, an SISO LTI filter and a conventional decimator. Hence, incompatible nonuniform filter banks could achieve perfect reconstruction via LTI filters, conventional samplers and block samplers without expanding the input-output dimension of a subsystem of linear dual-rate systems or converting the nonuniform filter banks to uniform filter banks. The main advantage of the proposed representations is to avoid complicated design of the circuit layout caused by connecting subsystems with large input-output dimension or a lot of subsystems together.     

静电梳齿驱动器薄膜变形反射镜

提出一种大冲程静电梳齿驱动器微机械薄膜变形反射镜,理论上研究了静电梳齿驱动器微机械薄膜变形反射镜的静电驱动力和变形位移与驱动电压的关系,分析了变形反射镜的驱动稳定性,比较了平板电容驱动器与纵向梳齿驱动器的驱动能力.结果表明,变形反射镜的静电驱动力和变形位移没有关系;在相同的面积下,纵向梳齿驱动器的驱动力比平板电容驱动器的驱动力大很多.     

A four-channel digital signal processor in 1.2-μm CMOS withon-chip D/A and A/D conversion serving four speech channels in anew-generation subscriber line circuit

The major component for a new-generation line circuit was designed and fabricated in a 1.2-μm CMOS technology. The circuit includes digital signal processing of receive (RX) and transmit (TX) signals as well as the analog front end of four subscriber lines to a PCM (pulse code modulation) digital exchange. The device operates on a single 5-V power supply. The four-channel digital signal-processor including the analog front ends is fabricated on a 40-mm² 1.2-μm CMOS die area. The DSP functions, the RX and TX filters, the decimator, the interpolator, and the A/μ-law transcoder are included as independent data paths, one for the TX and RX filters, one for the decimator, and another for the interpolator, the digital sigma-delta modulator, and the transcoder. The on-chip analog front end contains a notch filter to cancel the 12/16-kHz payphone signal, a switched-capacitor PDM A/D and D/A converter, and smoothing filters. On the first measured samples, the signal-to-distortion ratio is measured to be 33 dB at -45 dBmo for -7 dB gain setting     

一种类正余弦CIC滤波器

传统CIC滤波器由于其实现不需要乘法器和存储器,因此已在各种变采样率系统中得到了广泛的应用。但是传统CIC滤波器的通带失真较大,阻带衰减较小,而且其积分器工作在高采样率端,这很大程度限制了它在对性能要求较高的变采样率系统中的应用。而后来提出的各种CIC滤波器,如锐化CIC滤波器、ISOP-CIC滤波器和CIC-Cosine滤波器等,或者只改善通带特性,或者只改善阻带特性,或者积分器运行在高采样率端。本文在分析对比了传统的CIC滤波器、锐化CIC滤波器、ISOP-CIC滤波器和CIC-Cosine滤波器的频率特性的基础上,引入一种类余弦预滤波器和一种类正弦预滤波器,再加上多级级联的传统CIC滤波器,构成一种多级结构的类正余弦CIC滤波器。所引入的类正弦预滤波器和类余弦预滤波器分别用于减小CIC滤波器的通带失真和增大其阻带衰减。仿真结果表明,所提出的类正余弦CIC滤波器比传统的CIC滤波器、ISOP-CIC滤波器、CIC-Cosine滤波器都具有更小的通带失真和更大的阻带衰减。同时所引入的两级预滤波器工作在低采样率端,并且通过使用多相分解技术同样可使多级级联的CIC滤波器工作于低采样率端。      

Roundoff noise in multirate digital filters

The roundoff noise problem for multirate digital filters is difficult because rate changing inside the filter makes both scaling and roundoff noise calculation complicated. With a new multirate filter analysis technique, the transfer function between any two points inside a multirate filter can be easily found, thus, simplifies the scaling and noise calculation. This paper finds theL _P scaling and derives the roundoff noise expressions for fixed point implementations of the multistage decimator, interpolator, and multirate narrow-band low-pass filter. It is shown that the noise source at a low sampling rate stage is more important than that at a higher sampling rate stage. Methods to reduce output roundoff noise are discussed.This research was supported by NSF grant ECS 81-00453.     

A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems

An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a switched-current sigma-delta modulator (SISDM) and a digital decimator. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the oversampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class-AB memory cell are low power consumption and high dynamic range. Moreover, a new single-multiplier structure is presented to implement the finite-impulse-response (FIR) digital filters which are the major hardware elements in the decimator. For the various applications with different biosignal frequencies, the SDADC could be manipulated in different operating modes. The overall ADC has been implemented in a TSMC 0.18-mum 1P6M standard CMOS process technology. Without a voltage booster to raise the gate voltage of switches, measurement results show that the SISDM has a dynamic range over 60 dB and a power consumption of 180 muW with an input signal of 1.25-kHz sinusoid wave and 5-kHz bandwidth under a single 0.8-V power supply for electroneurography signals. In addition, the postlayout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without degrading by digital circuits     

Symmetry exploitation in digital interpolators/decimators

This correspondence extends the symmetric FIR filter algorithms of the previous work of the author to the computation of interpolators and decimators. We will show that the number of arithmetic operations in digital interpolation and decimation can be significantly reduced. As a result, we introduce a new class of efficient interpolator and decimator structures     

On sampling rate, analog prefiltering, and sufficient statisticsfor digital receivers

We consider the joint sequence estimation, timing and phase recovery for linear modulation. The paper differs from the classical ones in the sense that time-discrete algorithms suitable for fully digital receivers are discussed. Sufficient conditions are given such that the signal samples represent sufficient statistics. These conditions involve signal bandwidth, sampling/symbol rate and the analog prefilter characteristics. It is shown that the sampling rate need not be an exact multiple of the symbol rate, i.e., the samples can be taken from a free-running oscillator. All subsequent signal processing operations in the receiver then operate with the clock of this free-running oscillator. Timing recovery is then performed by a time-variant linear digital interpolator and a decimator. Carrier recovery and sequence estimation are performed at an average rate of one symbol per sample. The digital matched filter for this case is derived for an arbitrary colored noise spectrum     

Analysis and Demonstration of a Fast Tunable Fiber-Ring-Based Optical Frequency Comb Generator

Fiber-ring-based optical frequency comb generators are analyzed to understand their behavior and limitations. A numerical frequency-domain model is described for studying dispersion and other phase mismatch causing effects in the fiber ring cavity, as well as for predicting the spectral and temporal evolutions of the comb in time. The results from this analysis are verified with experimental measurements. A flat optical comb, with a terahertz span within a 6-dB power envelope and containing 100 comb lines, with a suppressed central comb line, is demonstrated. The comb shows an excellent coherence dependent on the phase noise from the radio frequency synthesizer that drives the comb generator. Improvement in the error correction loop also enables the comb spacing to be set at precise 12.5-MHz intervals without having to adjust the system. Fast frequency switching of the comb line spacing is demonstrated for the first time. The comb line spacing can be switched to any operation frequency with a resolution of 12.5 MHz between 6 and 12.5 GHz, as limited only by the microwave circuit used. The switching time is less than 1 s, and the spectral profile of the comb is maintained.