倒装芯片组装集成电路开封方法

倒装芯片组装集成电路的结构与常规封装不同,导致现行开封技术不完全适用于倒装芯片组装集成电路。对不同封装形式的倒装芯片组装集成电路结构分析,找出目前制约开封技术的关键因素。以陶瓷及塑封封装倒装芯片组装集成电路为例,运用热风枪、高温预处理、机械应力及化学腐蚀等方法,提出了一套适用性强、效率高的综合性倒装芯片组装集成电路开封工艺技术,并通过实例进行验证和总结。通过运用该技术可以有效解决倒装芯片组装集成电路的开封问题,为后续标准的修订及破坏性物理分析提供依据和帮助。     

Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.     

Thermal distribution calculations for block level placement in embedded systems

Reliability is a very important concern for the embedded systems. Thermal distribution has become an important reliability concern for today’s integrated circuits and these circuits are being used increasingly in embedded systems. In traditional design flows, the temperature of the chip is assumed to be uniform across the substrate. However, non-uniform thermal distribution can be a major source of inaccuracy in delay and clock skew computations, and can have an impact on elctromigration reliability and self-heating effects for today’s very deep submicron technology. Hence, it has become necessary to obtain design with uniform temperature distribution to ensure minimum temperature gradient and avoid hot spots across the chip area. This will minimise reliability problems during the operation of the chip. The uniform temperature distribution can be achieved by appropriate placement of circuit blocks during the physical design. In this paper, thermal distribution of single chip embedded system on silicon is discussed. The thermal distribution calculations require evaluation of switching activity factor of circuit blocks. This factor is determined by computing activities of the blocks based on the application software of embedded system.     

Cool Chips: Opportunities and Implications for Power and Thermal Management

Alongside innovative device, circuit, and microarchitecture level techniques to alleviate power and thermal problems in nanoscale CMOS-based integrated circuits (ICs), chip cooling could be an effective knob for power and thermal management. This paper analyzes IC cooling while focusing on the practical temperature range of operation. Comprehensive analyses of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies are presented. Unlike all previous works, this analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While chip cooling always gives performance gain at the device and circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and an associated cost that may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots.     

XD3301过温保护模块的设计

主要介绍了降压型(Buck)DC/DC专用集成电路XD3301的基本功能和特点,并给XD3301设计了一种CMOS工艺的高精度过温保护电路,通过芯片结温和三极管的阈值进行比较,当芯片结温高于三极管的阈值时,关断开关管;而当芯片结温低于三极管的阈值时,打开开关管,芯片正常工作。给出了过温保护模块具体的电路设计原理、计算方法,并用HSpice软件对结果进行了仿真验证。     

Asynchronous control of modules activity in integrated systems for reducing peak temperatures

The paper describes a new control method of integrated circuit (IC) modules activity in a modern processor design. The control method leads to improved frequency ability of integrated systems. The proposed solution, based only on computing flow modification, could be easily integrated into all future designs, ranging from a portable computing to a multi-core computing. A new approach to the thermal control method is described along with simulation results. An example of incorporation in current and future integrated circuits into mainstream designs is presented with exemplary algorithms and final simulation results.     

Dynamic depletion mode: an E/D MOSFET circuit method for improved performance

A new method of designing enhancement/depletion (E/D) MOSFET circuits, involving the dynamic or pulsed use of depletion-mode devices, is described. The method can result in improvements in performance and/or power in the design of memory, logic, and driver circuits. The method is compared with the standard approach to the design of E/D circuits. Several circuits designed by the method have been simulated by use of a numerical circuit analysis program and have been placed on an experimental test chip. Theoretical and experimental results are presented.     

Dynamically inserting, operating, and eliminating thermal sensors of FPGA-based systems

In this paper, a new thermal monitoring strategy suitable for field programmable logic array (FPGA)-based systems is developed. The main idea is that a fully digital temperature transducer can be dynamically inserted, operated, and eliminated from the circuit under test using run-time reconfiguration. A ring-oscillator together with its auxiliary blocks (basically counting and control stages) is first placed in the design. After the actual temperature of the die is captured, the value is read back via the FPGA configuration port. Then, the sensor is eliminated from the chip in order to release programmable resources and avoid self-heating. All the hardware of the sensor is written in Java, using the JBits API provided by the chip manufacturer. The main advantage of the technique is that the sensor is completely stand-alone, no I/O pads are required, and no permanent use of any FPGA element is done. Additionally, the sensor is small enough to arrange an array of them along the chip. Thus, FPGAs became a new tool for researchers interested in the thermal aspects of integrated circuits.     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

一种基于数字灰度的微显OLEDos的片上电路设计

介绍了高分辨率硅基微显OLED的特性和时间子场的数字灰度技术,基于单晶硅CMOS成熟技术,给出了一种片上电路设计方案,方案采用2管的数字像素电路,集成了行扫描电路及列数据驱动电路,经模拟仿真满足设计要求。     

三维集成电路中TSV的热特性研究

基于Comsol Multiphysics平台,通过使用有限元仿真对三维集成电路的硅通孔(TSV)模型进行了热仿真分析。分别探究了TSV金属层填充材料及TSV的形状、结构、布局和插入密度对三维(3D)集成电路TSV热特性的影响。结果表明:TSV金属层填充材料的热导率越高,其热特性就越好,并且采用新型碳纳米材料进行填充比采用传统金属材料更能提高3D集成电路的热可靠性;矩形形状的TSV比传统圆形形状的TSV更有利于3D集成电路散热;矩形同轴以及矩形双环TSV相比其他结构TSV,更能提高TSV的热特性;TSV布局越均匀,其热特性越好;随着TSV插入密度的增加,其热特性越好,当插入密度达6%时,增加TSV的数目对TSV热特性的影响将大幅减小。     

一种基于数字灰度的微显OLEDos的片上电路设计

介绍了高分辨率硅基微显OLED的特性和时间子场的数字灰度技术,基于单晶硅CMOS成熟技术,给出了一种片上电路设计方案,方案采用2管的数字像素电路,集成了行扫描电路及列数据驱动电路,经模拟仿真满足设计要求.     

Integrated electro-thermomechanical analysis of nonuniformly chip-powered microelectronic system

An integrated electrical, fluid flow and thermomechanical analysis is presented to study a product reliability and thermal management solution in an actual or nonuniform chip power distribution of an integrated circuit device in a realistic system application environment. This study aims to improve the existing limitations both on electrothermal analysis where simplified thermal boundary conditions is mostly used and on the current thermal and fluid flow analysis where uniform chip power is widely used to calculate the temperature. In this approach, the localized on-chip power distribution is obtained by using a transistor-level circuit model for simulating the interaction between the macro and functional blocks. A computational fluid dynamics analysis is used to calculate the fluid flow and heat transfer solution with a realistic thermal boundary conditions. To address the ultimate thermal induced mechanical stress and reliability effects on the chip-packaged assembly due to the nonuniform chip power distribution, finite element model is employed for the sequential steady-state heat transfer and mechanical analysis. The results are then discussed and specifically compared with the solutions based on the uniform chip power conditions.     

Synchronization circuit performance

Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two independently timed regions. The mean time between failures (MTBF) is given. These effects can be explained by extending the existing theory to take account of initial offsets, and we propose a new, more accurate, formula. Synchronizer performance depends on achieving a high reliability of synchronization together with a short time. We show that commonly used circuits, such as the jamb latch, do not produce the best compromise for very high reliability applications, and that a better circuit can be designed. In order to confirm that thermal noise does not influence the MTBF against synchronization-time relationship, we have devised an experiment to measure noise in an integrated CMOS bistable circuit. We show that the noise exhibits a Gaussian distribution, and is close to the value expected from thermal agitation     

LDO中过温保护电路的设计

LDO是一个微型的片上系统,他包括调整管、采样网络、精密基准源、差分放大器、过流保护、过温保护等电路。分析了LDO中过温保护电路的设计,主要介绍了LDO中双极型过温保护电路和CMOS过温保护电路。由于双极器件开发早、工艺相对成熟、稳定,而且用双极工艺可以制造出速度高、驱动能力强、模拟精度高的器件,适用于高精度的模拟集成电路。因此,双极型集成稳压器应用广泛,其设计技术和制造工艺比较成熟和完善。但双极型过温保护电路本身存在热振荡的问题。给出一种新型的CMOS过温保护电路,他具有温度迟滞功能,有效地避免了芯片出现热振荡。     

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits will be needed to extend circuit complexity to the range currently dominated by silicon     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

基于强化学习的多核芯片动态功耗管理框架

多核芯片可以为移动智能终端提供强大算力,但功耗和温度问题始终制约着其性能表现。针对这个问题,该文提出了一种基于强化学习的多核芯片动态功耗管理框架。首先,建立了一个基于GEM5的多核芯片动态电压频率调节仿真系统。然后,采用了一种考虑CMOS芯片物理特性的功耗模型构建方法以实现在线实时功耗监测。最后,设计了一种面向多核芯片的梯度式奖励方法,并使用深度Q神经网络(Deep Q Network, DQN)算法对多核芯片的功耗管理策略进行学习。仿真结果表明,相比于常规的Ondemand,MaxBIPS方案,该文所提出的框架分别实现了2.12%, 4.03%的多核芯片计算性能提升。     

两种低功耗新型过温保护电路的设计

电源管理芯片中过温保护电路用来检测芯片的温度。当温度过高时,过温保护电路输出保护信号,使芯片停止工作,以免温度过高而损坏芯片。为了实现上述过温保护电路功能,提出了两种新型的过温保护电路,不但能够精确地检测芯片的温度,并且功耗很低。采用0．5μm N-阱CMOS工艺的方法,进行电路设计,并使用CadenceSpectre工具进行了仿真实验验证。仿真实验结果表明两种电路仅消耗3μA的电流就能够实现精确的温度检测,其具有较强的适应性,高灵敏度和高精度的特点,应用前景比较广泛。     

含全耦合电感电路的求解

分析动态电路既可以应用拉普拉斯变换方法,也可采用时域分析方法。通过分析含全耦合电感电路,得出流入耦合电感的电流有可能发生跃变的结论,该电流不是电路的状态变量。对含全耦合电感电路的求解以拉普拉斯变换方法为宜。如果采用时域分析方法,则应采用含全耦合电感电路的等效电路来求解。上述分析结果可供讲授电路理论的教师参考。