手动探针测试台的自动化设计

介绍了一种对ST-103A型手动探针测试台进行自动化改造的设计方案。在原设备的基础上,引进步进电机代替原来的手轮控制;其次,还引进了摄像头和视频采集卡技术实现对探针台的实时监控;另外,通过VC++编写上位机友好界面既提高了控制精度,又使得控制更为方便。经测试,改造后的探针测试台能实现高精度的全自动化控制。     

欧洲MEMS工业一瞥

欧洲处在微机电系统(MEMS)工业的最前沿，有大约 100家工厂，MEMS 设备工业也在日益成熟。共有从业人员4000多人，2000年的销售额总数达 10亿美元，每年处理的圆片超过50万片。而其基础设施的生产能力为80万等效4英寸圆片。一半的欧洲MEMS公司处理100mm圆片，但是有升级到150mm(25%是处理150mm圆片)的趋势，并且有 3项 MEMS设备工程将处理200mm圆片。MEMS正在作为欧洲的新兴工业出现,每年的销售额达到10亿美元。然而, 必须克服封装和测试的挑战,并且需要更好地获取生产设备。MEMS工业链MEMS的生产设备的生产日益活跃，如：双面…     

简讯

J923171 低温多探针测试台针对我所在研制碲镉汞(HgCdTe)器件过程中,为满足中测筛选芯片的需要,我们研制成低温多探针测试台。该测试系统能在低温下对半导体基片上的芯片的光电参数一一进行测试,从而筛选出合格芯片。对需在78K温度下筛选的各种半导体基片都适用。如:     

Touchdown Technologies推出用于高级DRAM测试的全晶圆探针

半导体测试公司惠瑞捷(Verigy)旗下全资子公司Touchdown Technologies推出了其1Td300全晶圆探卡,这是该公司首款用于高级DRAM存储器件单次触压、高容量测试的探卡。该产品能够对300 mm或200 mm晶圆进行高并行测试(highly parallel tesTIng)。每探针只需要2g压力就能够测试整个300 mm晶圆,堪称业界最低的探针压力,所需压力不到市面上同类产品的一半。1Td300探卡提供了双重优势,不仅能够降低对被测晶圆和整个测试台的压力,同时允许更高的引脚数,以拓展半导体测试范围。《国际半导体技术蓝图》(ITRS)预计,到2011年,DRAM的多     

雷达数字电路板测试台的开发与应用

电路板测试台是一种自动化数字电路故障测试设备,能快速、准确地将故障定位到芯片。本文介绍了测试台的基本组成、硬件设计、软件设计及其应用,该测试台在测试接口上采用多种电路板接口,在测试通道上采用总线接口通道和探针通道并存的方式。     

多片干法蚀刻设备蚀刻均匀性工艺优化研究

对于制造集成电路芯片的多片生产设备而言,圆片间均匀性是评价工艺优劣的重要指标,可以利用正交试验方法来优化均匀性工艺.使用装载容量为18个150 mm圆片的AME8110干法蚀刻设备,利用正交试验方法进行干法蚀刻二氧化硅试验.通过直观分析,得到影响干法蚀刻均匀性的较优因素组合;通过方差分析,得到各因素对均匀性影响的显著性和可信度;通过工艺综合分析,得到各因素水平的选择原则和满足圆片间均匀性指标要求的优化工艺.按照优化工艺测试的圆片间蚀刻均匀性为3.93％.正交试验分析方法同样适用于其他多片生产设备和单片生产设备的工艺优化.     

大圆片样品方块电阻测试及径向等高线图的绘制

本文用微机控制四探针测试系统,按着分区等差方法计算的连续点,描绘出半导体大圆片样品方块电阻的径向等高线图.     

用于高级DRAM测试的单次触压、全晶圆探针

1Td300全晶圆探卡是一款用于高级DRAM存储器件单次触压、高容量测试的探卡，该产品使用专有的全晶圆架构和基于MEMS的ACCU-TORQ弯曲探针进行非常平滑的单次触压测试。该产品能够对300mm或200mm晶圆进行高并行测试（highly parallel testing）。每探针只需要2g压力就能够测试整个300ram晶圆，1Td300探卡提供了双重优势，不仅能够降低对被测晶圆和整个测试台的压力，同时允许更高的引脚数，以拓展半导体测试范围，     

自动探针测试速度的提高方法与实现途径

对探针台测试速度的提高方法进行了讨论 ,且论述了这种方法在TZ— 10 7型自动探针测试台的实际应用与实现途径。     

圆片级组装、测试一体化的后道工艺

<正> 为了在半导体后道制造工艺中有效地应用摩尔比例缩小定律,必须要有一体化的圆片级封装工艺,并且,它可以以圆片的形式进行测试、老化和其它操作。到目前为止,已有多种圆片级封装技术的报导,但几乎都没有涉及到圆片级的测试和老化问题。一种新的技术可以使圆片级 CSP(芯片尺寸封装)、圆片级测试和最终组装一体化。其核心技术是直接在圆片上制作微弹簧接触器。这类接触器已被25个以上半导体厂家和测试工厂广泛用于高平行度探针卡上。圆片上的接触器,在老化和测试中被用作柔性弹性接触接口,在组装中被用作一级互连——焊接或插接芯片到衬底上。     

1034探针台平面电机功放部件的维修

在1034探针台中，驱动承片台在X－Y方向运动的平面电机功率放大部件是该设备的核心部件，其性能的好坏直接关系到探针台的性能。本文拟从简述平面电机的原理入手，对该功放部件的性能、测试方法和维修作一讨论。     

5G毫米波端到端性能测试技术研究

面向5G毫米波大规模阵列天线基站,创新提出了端到端性能测试系统。从技术原理、硬件架构、系统校准这几个维讨论了如何完成毫米波基站的性能验证。依据3GPP定义的信道模型,仿真了暗室静区中的最关键指标角度功率谱相似度百分比,并且给出了指标建议。     

Fast electromigration wafer mapping for wafer fab process monitoring and improvement

In this work, a set up for fast wafer level electromigration (WL-EM) is developed with the use of a standard electrical analyser, a semi-auto probe station with a hot chuck, and a PC. EM tests on multiple test structures are carried out simultaneously and tests are done at multiple locations (EM mapping) across the wafer. Measured data are imported into MS EXCEL and analysed with a macro automatically. Good correlations are demonstrated between the fast WL-EM test and classical package level EM at 0.1% failure rate. For several years reliable EM monitoring charts are created with the fast WL-EM set up. The fast EM mapping test does not only exploit the advantages of fast WL-EM test in terms of short throughput time and low cost (without packaging) for process monitoring, the additional information on EM performance across the wafer makes the test extremely valuable for process improvement.     

Φ52mm×1.8mm薄园片锗单晶电阻率的测试

文章对Φ52mm×1.8mm薄园片锗单晶的电阻率进行测试,通过引入锗园片的厚度修正系数和直径修正系数,得到锗园片中心电阻率是23.51Ω.cm,园片边缘为27.16Ω.cm,不均匀性15.53%,提高了电阻率测定的准确性。     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

晶圆级导通电阻测试精度的改进方法

针对晶圆级导通电阻测试误差过高,满足不了低压金属氧化物半导体场效应晶体管(MOSFET)毫欧级导通电阻的测试精度要求,给产品晶圆测试规范的制定及品质监控带来困扰的问题,提出了晶圆级导通电阻测试精度的改进方法。基于开尔文法电阻测试理论,具体分析了晶圆级导通电阻测试原理,且得出其测试精度不高的根本原因是减薄背金后粗糙不平的硅片背面与测试机的承片台的非充分接触而引入了毫欧级接触电阻。提出3种相应改进测试精度的方法,单相邻芯片辅助的测试方法、双相邻芯片辅助的测试方法和正面漏极测试窗的测试方法。经过验证,3种方法均能将毫欧级导通电阻测试误差控制到小于10%,实现低压MOSFET晶圆级导通电阻参数的有效监测。     

数字化红外探测器的读出电路晶圆测试系统研究

数字化红外探测器的读出电路晶圆测试是评价晶圆的重要环节。在现有探针台测试设备的基础上，研制了一块电路板装置。它既可驱动晶圆工作，也可将不同形式的数字化输出信号转换为统一的数字图像传输格式,而且测试过程中可对电路板参数进行设置。首先对红外探测器读出晶圆测试系统进行了介绍，然后对研制的测试电路板装置进行了原理分析。最后将此电路板进行硬件实现，并编写了内部测试程序，完成了功能验证。对差分输出和单路输出两种形式的晶圆进行了测试，其结果与晶圆低温下的测试结果一致，数据准确可靠。此外电路装置有100个输入接口，可重复编程，支持24bit及以下输出位宽数字化晶圆的测试，使测试系统具有更高的兼容性和灵活性。     

金属化布线晶片级测试系统

晶片级测试方法是半导体器件（ＶＬＳＩ）金属化可靠性试验中的一种新方法,本研究在现有设备的基础上进行了一系列的设计和改进,建立了一套同微机控制的晶片级金属化电徒动测试系统,为金属化可靠性测试和在线监测的研究奠定了良好的基础。     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Evaluation and optimization of large area III-V epitaxial thickness uniformity using a Fabry-Perot microcavity test structure

We report a technique for simply and conveniently measuring epilayer thickness uniformity to 0.5% over an entire wafer. The technique requires epitaxial growth of a Fabry-Perot microcavity test structure. Mapping is performed by measuring the wavelength-dependent optical reflectivity at different points on the wafer and then fitting the reflectivity data to deduce the thickness uniformity. The mapping technique was used to determine the optimal growth conditions in a vertical rotating disk reactor that resulted in better than ±1% uniformity over a 2 inch wafer. The high precision of the optical reflectivity mapping technique can provide information not easily obtained with other techniques. For example, we show that the presence of wafer flat adversely affects the thickness uniformity.