TMS320C6455的硬件资源分析

TI公司最新的高端定点数字信号处理（DSP）芯片TMS320C645x可实现更高性能、更精简代码、拥有更多片上存储器以及超高带宽的集成外设,应用范围更加广泛,是C641x DSP开发人员寻求升级的理想之选。介绍了TMS320C6455的硬件配置、初始化配置以及外围设备资源,并与该公司另一款应用广泛的DSP芯片TMS320C6416T的硬件资源进行了对比分析,为C641x DSP开发人员升级到TMS320C6455提供有效的参考帮助。     

TMS320VC55x系列DSP在线烧写方法研究

TMS320VC55x系列DSP是TI公司在TMS320C54x基础上推出的新一代低功耗DSP.由于该系列DSP没有片内Flash.所以程序的加栽方法是必须解决的问题.阐述了TMS320VC55x系列DSP的片外Flash在线编程方法,给出了系统的硬件连接方法和烧写程序,并研究了自举引导的实现方法.     

TMS320C 54x系列DSP应用初探

本文介绍了TMS320C54x系列DSP的存储结构,详细讨论了存储器和存储空间的映射关系,分析了存储空间的配置方法,并结合实例给出了C5410型DSP的存储器映射关系和链接配置文件。     

TMS320C55x系列DSP与SDRAM接口设计

主要讨论TMS320C55x系列DSP（数字信号处理器）与SDRAM（同步动态随机存取存储器）的接口设计,以及软件编程。首先介绍了TMS320C55x系列的EMIF以及EMIF的外接存储器类型。解释了为什么只讨论与SDRAM的接口,其次介绍了SDRAM的操作方法,并给出了硬件连接图,最后给出了软件操作方法以及部份程序。     

基于TMS320C54x DSKplus的实时TCM语音编解码算法的实现

描述了基于TMS320C54x数字信号处理器的TCM语音压缩编码系统。该系统是在TMS320C54xDSP入门套件（DSK,DSP Starter Kit）板上实现,充分发挥了芯片的专用硬件逻辑、专业化的指令以及板上TLC320AC01模拟接口语音处理系统。有效而快速地完成了TCM语音压缩系统的模拟,并给出相应的实验结果。     

实时跟踪系统中的DSP软件优化方法

TI的TMS320C6x系列DSP具有独特的甚长指令字（VLIW）结构,DSP软件的执行效率在某种程度上决定了硬件功能的实现。在用DSP进行实时跟踪系统的设计时,软件的执行效率将直接影响整个系统的实时性。笔者归纳了基于DSP的实时跟踪系统中软件优化的方法,包括DSP关键字和内联函数的使用、数据打包处理、软件流水线以及编译器选项的设定。采用这些方法对DSP软件进行优化,解决了系统的弱实时性问题,同时也提高了整个系统的可靠性。     

TMS320VC55x系列DSP在线烧写方法研究

TMS320VC55x系列DSP是TI公司在TMS320C54x基础上推出的新一代低功耗DSP。由于该系列DSP没有片内Flash,所以程序的加载方法是必须解决的问题。阐述了TMS320VC55x系列DSP的片外Flash在线编程方法,给出了系统的硬件连接方法和烧写程序,并研究了自举引导的实现方法。     

基于EDMA实现TMS320C64X与FPGA的数据传输

结合TMS320C64XDSP＋FPGA信号处理平台,简述了TMS320C64X DSP的硬件结构,重点介绍直接存储器访问（EDMA）的硬件结构和配置方法。数据经现场可编程门阵列（Field-Pro-grammable Gate Array,FPGA）及DSP外部存储器接口（EMIF）由EDMA传输到数字信号处理器（DSP）片内,传输过程不需要CPU干预,并且采用乒乓缓冲结构,CPU同时可以进行数据处理,提高了数据传输、处理的速度,保证了实时性。     

新品之窗

MCU/DSPTMS320C6418:DSP 德州仪器公司日前推出新型基于TMS320C64x核的高性能600MHz DSP TMS320C6418,它在性能、存储器、外设和价格上有较好的平衡组合,用在通信、软件无线电和地面以及卫星广播系统。 C6418 DSP在600MHz时BDTImark2000的基准评分为5480。C6418具有512KBL2存储器,Viterbi协处理器(VCP)每秒进行24亿次     

基于TMS320DM642的H.264视频解码器设计

给出了基于TMS320DM642的H.264视频解码器的设计,并详细讨论了解码器的硬件结构、算法优化、存储器分配以及DSP的PCI驱动程序的编制.     

DSP的并行处理方法

TI公司TMS320C6x和AD公司ADSP2106x是目前业界使用广泛的数字信号处理嚣(DSP)．本文详细地介绍了利用TMS320C6x的接口HPI、接口McBSP以及ADSP2106x的Link接口分别组成并行DSP处理系统的方法．同时介绍了这些方法的优缺点。     

TMS320C54x Simulator文件格式及其应用

详细介绍了TMS320C54x Simulator环境的文件格式及其文件加载步骤,以及如何将BMP或JPEG格式灰度图像转换为能够使TMS320C54x Simulator识别的格式文件.实例应用表明此方法能够将图像信息加载到TMS320C54x Simulator环境中,进行相应的图像处理.     

MPEG-4 Video and Image Coding on Digital Signal Processors

The emerging MPEG-4 standard encompasses a wide variety of applications, many of which are suitable for implementation on a Digital Signal Processor (DSP). In particular, consumer products with embedded multimedia capability, such as set-top boxes and wireless communicators, are suitable for DSP-based implementation. With a programmable approach, various algorithmic tradeoffs can be made, based on processing capability. For best performance, careful attention must be paid to memory allocation, data transfer, and ordering of instructions to best match the DSP architecture. We discuss implementing simple profile MPEG-4 video on the low-power TMS320C54x, core profile on the TMS320C6x, and scalable texture profile, which could be implemented on either processor family.     

High VelociTI processing [Texas Instruments VLIW DSP architecture]

The Texas Instruments VelociTI architecture is a very long instruction word (VLIW) architecture. The TMS320C6x family of digital signal processors (DSPs) is the first to employ the VelociTI architecture, with the TMS3206201 (C6201) being the first device in this family. The C6201 is based on the fixed-point TMS320C62x (C62x) CPU. This article describes the VelociTI VLIW architecture and discusses the C62x, C67x, C6201, and the VelociTI development tools. An overview of the VelociTI including architectural principles, data path, instruction set, and pipeline operation is presented, and both the C62x fixed-point CPU and the C67x floating-point CPU are described. A summary of the C62x benchmark performance is also presented. The chip-level support outside the CPU that allows the C6201 to operate in a variety of high-performance DSP environments is also described. An overview of the C6x development environment is also given, demonstrating the breadth of the development environment and illustrating the programming methodology. The article concludes with a performance analysis of the C compiler     

TMS320C64x的16-bit Flash加载的可行性分析与实现

简要介绍TMS320C64x系列数字信号处理器(DSP)Flash加载的基本原理,详细论述TMS320C64x DSP与16-bit Flash接口的设计方法及用该方案加载的可行性及优点,给出.out文件到可供软件片上烧写的数据文件的编写方法.     

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.     

基于TMS320C6713的USB数据传输系统设计

介绍了基于TMS320C6713的USB数据传输系统。该系统以TMS320C6713作为主控制器,通过CY7C68001USB控制器连接TMS320C6713与PC主机,克服了传统的数据传输量小,传输速度慢的缺点,能更好地满足大容量数据的传输要求。在此详细阐明了系统的硬件设计方案和软件设计思想,并进行实现。结果证明,研制的系统具有传输速率高,可靠性好的优点。     

TMS320C64x系列 DSP的软件优化技术

较为详细地描述了TMS320C64x系列DSP芯片软件编程优化设计方法的设计与实现方法,提出优化设计方法中需要注意的问题及其解决方法,并通过仿真验证,较全面地证明了该优化设计方法的有效性和实用性,以期为高速实时系统设计提供一种可行的解决方法。