Reactive ion etching and characterization of p-silk ultra low-k film

Reactive ion etch (RIE) of p-SiLK, a spin-on polymer based ultra low-k (ULK) material with a k value of /spl sim/2.2 was characterized and its influence on electrical yield and dielectric breakdown is presented here. Material characterization was done using blanket films after curing and the effect of exposure to different conventional plasma etch gas mixtures was studied for surface composition, roughness and dielectric constant. Trench etch process was developed for 130-nm technology node for single damascene process integration. Dual hard mask approach was taken and two etch schemes viz., etching under hardmask and etching under photoresist were evaluated. In both schemes, trench etch profiles were near vertical and critical dimension (CD) control was within 10%. RIE lag and the carbon depletion at the sidewalls were found to be insignificant confirming acceptable etch process performance. Etching under photoresist scheme was found advantageous in terms of trench profile for isolated structures, reduced cycle time making the process cost effective and reduced post-CMP defects. However, from the comparison of electrical test results, etch under hardmask scheme showed higher electrical yield and better performance than etch under PR scheme. Although trench sidewalls were exposed to plasma during both schemes, sidewall damage did not contribute to overall leakage. The RIE process developed and the characterization results have confirmed the compatibility of material and RIE process for successful process integration.     

Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density

We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H₂ anneal) further reduce the CD to 13 nm.     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon(a-Si) hardmask is presented.SCI(NH_4OH:H_2O_2:H_2O),which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate(TEOS) hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric be...     

Controlling resist thickness and etch depth for fabrication of 3D structures in electron-beam grayscale lithography

In many applications such as optoelectronic devices, three-dimensional (3D) structures are required. Examples include photonic band gap (PBG) crystals, diffractive optical elements, blazed gratings, MEMS, NEMS, etc. It is known that the performance characteristics of such structures are highly sensitive to their dimensional fidelity. Therefore, it is essential to have a fabrication process by which such 3D structures can be realized with high dimensional accuracy. In this paper, practical methods to control thickness of the remaining resist and etch depth, which may be employed for fabrication of such 3D structures using grayscale electron-beam lithography, are described. Through experiments, explicit control of the remaining resist thickness and etch depth at the resolution of 20 nm for the feature sizes of 0.5 μm and 1 μm has been successfully demonstrated. Also, the 1:1 ratio of silicon to resist etching rates was achieved for transferring the remaining resist profile onto the silicon substrate.     

SiLK™ etch optimization and electrical characterization for 0.13 μm interconnects

This paper is focused on the optimization of reactive ion etching (RIE) process of low-k polymeric spin-on dielectric (SOD) material, SiLK™ (Trade mark of Dow Chemical, USA), for 0.13 μm Cu-low-k interconnects technology and subsequent electrical characterization of the metallization. Damascene metallization of SiLK™ film was integrated with dual hardmask scheme and “trench first” approach. Etch processes for single damascene metal trench and dual damascene via and metal2 trench structures were developed and evaluated. Effect of SiN and SiC films used as one of the hard mask layers and copper cap layers for single and dual damascene formation were also evaluated. The advantages of using SiC over SiN layer as one of the (bottom) dual hardmask layers were demonstrated through the results of electrical performance. Integration issues related to process development were analyzed and discussed. Electrical and reliability performance of testing vehicles associated to different etch criteria were studied. Electrical yield of >90% was obtained for the structures under study, which indicated the wide process margin. The consistency of processes was further demonstrated through the successful integration of eight metal layers with SiLK™ dielectric film.     

Experimental investigation of the impact of LWR on sub-100-nm device performance

Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.     

Rigorous diffraction simulations of topographic wafer stacks in double patterning

Double patterning is regarded as a potential candidate to achieve the 32 nm node in semiconductor manufacturing. A key problem for a standard litho-etch–litho-etch (LELE) double patterning process is to evaluate and tackle the impact of the wafer topography resulting from the hardmask pattern on the second lithography step. In this paper, we apply rigorous electromagnetic field (EMF) solvers to investigate the wafer topography effects. At first, the studied 3D mask is split into two masks. The topography resulting from the exposure with the first split mask is described by a patterned hardmask. Based on that, the bottom antireflective coating (BARC) thickness of the second wafer stack is optimized. Alternatively, a two beam interference and the full diffraction spectrum of the second mask are used as the illumination of the wafer stacks, respectively. Finally, simulated 3D resist profiles for different BARC thicknesses are shown. The importance of wafer topography impact, the optimization of topographic wafer stacks, and the possible solutions to compensate for the impact of the wafer topography are discussed.     

A novel approach for the patterning and high-volume production of sub-40-nm gates

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility.     

A simple method for high yield fabrication of sharp silicon tips

A simple, high yield, method for the fabrication of sharp silicon tips is described. A triangular etch mask design is used to ensure that the tip forms with a single point. An anisotropic wet etch gives rise to a tip that continues to “self-sharpen” after the etch mask is released. The tip geometry comprises three converging {1 1 3} planes towards the apex with {3 1 3} planes forming at the base. The apex of each tip typically has a radius of curvature of <5 nm, which can be reduced to <2 nm by a subsequent oxide sharpening process. Tips of this kind have been successfully integrated into the fabrication of atomic force microscopy probes.     

Fullerene Resist Materials for the 32 nm Node and Beyond

Current resist materials cannot simultaneously meet the sensitivity, resolution and line width roughness (LWR) requirements set out by the International Technology Roadmap for Semiconductors (ITRS) for the 32nm node and beyond. Here we present a fullerene‐based, chemically amplified resist system, which demonstrates the potential to fulfill these requirements for next generation lithography. A chemically amplified fullerene resist was prepared, consisting of the derivative MF07‐01, an epoxide crosslinker, and a photoacid generator, such as triarylsulfonium hexafluoroantimonate. The sensitivity of this resist was shown to be between 5 and 10 µC cm^?2 at 20 keV for various combinations of post‐application bake and post‐exposure bake conditions. Using 30 keV electron beam exposure, sparse patterns with 15 nm resolution were demonstrated, whilst for dense patterns a half‐pitch of 25 nm could be achieved. The LWR for the densely patterned features is ～4 nm. The etch durability of the fullerene CA system was shown to be comparable to that of SAL601, a common novolac‐based commercial resist, at almost four times that of silicon.     

Nanoimprint lithography resist profile inversion for lift-off applications

A method is described in which the tapered features that are inherent to nanoimprint lithography are inverted to allow successful lift-off. A mold of the relief is created by in-filling the imprinted resist with hydrogen silsesquioxane (HSQ) before selectively removing the resist with O₂ plasma. Nanoscale etch masks have been created by lift-off from the negative HSQ profile and used to create high-aspect-ratio structures in materials that are hard to plasma etch.     

Effects of CH2F2 and H2 flow rates on process window for infinite etch selectivity of silicon nitride to ArF PR in dual-frequency CH2F2/H2/Ar capacitively coupled plasmas

The process window for the infinite etch selectivity of silicon nitride (Si₃N₄) layers to ArF photoresist (PR) and ArF PR deformation were investigated in a CH₂F₂/H₂/Ar dual-frequency superimposed capacitive coupled plasma (DFS-CCP) by varying the process parameters, such as the low frequency power (P_LF), CH₂F₂ flow rate, and H₂ flow rate. It was found that infinitely high etch selectivities of the Si₃N₄ layers to the the ArF PR on both the blanket and patterned wafers could be obtained for certain gas flow conditions. The H₂ and CH₂F₂ flow rates were found to play a critical role in determining the process window for infinite Si₃N₄/ArF PR etch selectivity, due to the change in the degree of polymerization. The preferential chemical reaction of hydrogen with the carbon in the hydrofluorocarbon (CH_xF_y) layer and the nitrogen on the Si₃N₄ surface, leading to the formation of HCN etch by-products, results in a thinner steady-state hydrofluorocarbon layer and, in turn, in continuous Si₃N₄ etching, due to enhanced SiF₄ formation, while the hydrofluorocarbon layer is deposited on the ArF photoresist surface.     

Fabrication of submicrometre resist patterns using an edge-defined technique

An edge-defined technique for the fabrication of submicrometre resist patterns is described. The technique consists of resist pattern fabrication, deep UV hardening, plasma deposition, spin coating of resist, developing back, and wet etch. A 100 nm line in 1.2 ?m-thick resist layer is obtained with essentially vertical walls.     

Electron cyclotron resonance plasma etching of HgTe-CdTe superlattices grown by photo-assisted molecular beam epitaxy

In order to form HgTe-CdTe superlattice diode arrays, a well-controlled etch process must be developed to form mesa structures on HgTe-CdTe superlattice layers. Wet etch processes result in nonuniform, isotropic etch profiles, making it difficult to control etch depth and diode size. In addition, surface films such as a Te-rich layer may result after wet etching, degrading diode performance. Recently, a dry etch process for HgTe-CdTe superlattice materials has been developed at Martin Marietta using an electron cyclotron resonance plasma reactor to form mesa diode structures. This process results in uniform, anisotropic etch characteristics, and therefore may be a better choice for etching superlattice materials than standard wet etch processes. In this paper, we will present a comparison of etch processes for HgTe-CdTe superlattice materials using electron microscopy, scanning tunneling microscopy, surface profilometry, and infrared photoluminescence spectroscopy to characterize both wet and dry etch processes.     

Properties of spin-on glass as an insulator for InP metal-insulator-semiconductor structures

The application of Futurrex IC1-200 spin-on glass as an insulator for InP metal-insu-lator-semiconductor (MIS) structures including InP MIS capacitors and InP MIS field-effect transistors (MISFET’s) was investigated. Preliminary measurements of the elec-trical properties of the spin-on glass were performed using Si MIS structures with the spin-on glass insulator layer. It was found that the spin-on glass which is subjected to a final curing treatment utilizing a rapid-thermal annealing at 600° C for 5 sec in a O₂ ambient exhibits the best electrical properties. However, it was demonstrated by sec-ondary ion mass spectroscopy that when done on InP, the 600° C rapid-thermal an-nealing resulted in the outdiffusion of indium and phosphorus into the spin-on glass. The change in the spin-on glass electrical characteristics due to this outdiffusion re-sulted in an instability in the InP MISFET operation.     

Siloxane Copolymers for Nanoimprint Lithography

Presented here is the novel use of thermoplastic siloxane copolymers as nanoimprint lithography (NIL) resists for 60 nm features. Two of the most critical steps of NIL are mold release and pattern transfer through dry etching. These require that the NIL resist have low surface energy and excellent dry‐etching resistance. Homopolymers traditionally used in NIL, such as polystyrene (PS) or poly(methyl methacrylate) (PMMA), generally cannot satisfy all these requirements as they exhibit polymer fracture and delamination during mold release and have poor etch resistance. A number of siloxane copolymers have been investigated for use as NIL resists, including poly(dimethylsiloxane)‐block‐polystyrene (PDMS‐b‐PS), poly(dimethylsiloxane)‐graft‐poly(methyl acrylate)‐co‐poly(isobornyl acrylate) (PDMS‐g‐PMA‐co‐PIA), and PDMS‐g‐PMMA. The presence of PDMS imparts the materials with many properties that are favorable for NIL, including low surface energy for easy mold release and high silicon content for chemical‐etch resistance—in particular, extremely low etch rates (comparable to PDMS) in oxygen plasma, to which organic polymers are quite susceptible. These properties give improved NIL results.     

Development of metal etch mask by single layer lift-off for silicon nitride photonic crystals

We present a method for fabrication of nanoscale patterns in silicon nitride (SiN) using a hard chrome mask formed by metal liftoff with a negative ebeam resists (maN-2401). This approach enables fabrication of a robust etch mask without the need for exposing large areas of the sample by electron beam lithography. We demonstrate the ability to pattern structures in SiN with feature sizes as small as 50 nm. The fabricated structures exhibit straight sidewalls, excellent etch uniformity, and enable patterning of nanostructures with very high aspect ratios. We use this technique to fabricate two-dimensional photonic crystals in a SiN membrane. The photonic crystals are characterized and shown to have quality factors as high as 1460.     

微光机械振动传感器的设计与制作

采用旋涂和干法刻蚀技术,制作了一种新型有机集成微光机械振动传感器,其主要结构是由在硅基上制作的聚甲基丙烯酸甲酯(PMMA)悬臂梁和光波导集成光路组成,探测光路采用强度调制型开环差分探测,利用光-机转换功能,实现对微小振动量的检测。通过对该器件结构参数的优化设计和幅频特性分析表明,所制备的器件具有灵敏度高、线性度好、抗电磁干扰、工艺简单、成本低等优点。