Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson’s equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.     

Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs

A new analytical model for the subthreshold swing of nanoscale undoped trigate silicon-on-insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed, based on the channel potential distribution and physical conduction path concept. An analytical model for the potential distribution is obtained by solving the three-dimensional (3-D) Poisson’s equation, assuming a parabolic potential distribution between the lateral gates. In addition, mobile charges are considered in the model. The proposed analytical model is investigated and compared with results obtained from 3-D simulations using the ATLAS device simulator and experimental data. It is demonstrated that the analytical model predicts the subthreshold swing with good accuracy for different lengthes, thicknesses, and widths of channel.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Effects of Dummy Gate on Breakdown and Degradation of LDMOSFETs

For the first time, the effects of dummy-gate geometry and bias on breakdown and degradation of LDMOSFETs are quantified both theoretically and experimentally. First, the effects of dummy-gate geometry and bias are analyzed numerically by using a 2-D physical device simulator. Second, the simulated 2-D effects are approximated by a ldquodummy-gate chargerdquo in 1-D analytical solutions. Third, the 1-D analytical solutions are calibrated against breakdown and degradation characteristics measured on LDMOSFETs of different dummy-gate geometries and biases. The validated solutions can then serve as the basis for optimizing the design and operation of LDMOSFETs with the best tradeoff between performance and reliability.     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

Number and density of states in quantum semiconductor structures

Pushed by the semiconductor industry to achieve greater speed and functionality, device dimensions are becoming sufficiently small to exhibit prominent quantum mechanical effects. In addition, devices are now being developed that utilize these quantum effects. The number and density of states are fundamentally important in the operation of any quantum device. Traditionally in a classroom setting, one-dimensional (1-D), two-dimensional (2-D), and three-dimensional (3-D) continuum approximations are presented to analyze the quantum wire, well, and box, respectively. As shown in this paper, the exact number and density of states can be straightforwardly calculated by students for real semiconductor quantum structures. These results clearly illustrate the overall true 3-D form of each of these structures. These correct calculations also reveal an overestimation in the number of states when using the continuum approximations     

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

An improved analog electrical performance of submicron Dual-Material gate (DM) GaAs-MESFETs using multi-objective computation

In this paper, new modeling and optimization approaches are proposed to improve the electrical behavior of the submicron Dual-Material-gate (DM) Gallium Arsenide (GaAs)-MESFETs for analog circuit applications. The electrical properties such as current-voltage characteristics, transconductance, output conductance and drain to source resistance of the device have been ascertained and mathematical models have been developed. The proposed mathematical models are used to formulate the objective functions, which are the pre-requisite of genetic algorithm. The problem is then presented as a multi-objective optimization one, where the electrical parameters are considered simultaneously. Analog electrical parameters are also built for the three points sampled from the different locations of the Pareto front, and a discussion is presented for the Pareto relation between the small signal performances (analog behavior) and the design parameters. Therefore, the proposed technique is used to search for optimal electrical and dimensional parameters to obtain better electrical performance of the device for analog circuit applications. The proposed models have been validated by comparison with 2-D numerical simulations (SILVACO); the observed agreement with numerical simulations is quite good.     

A two-dimensional analytical subthreshold behavior analysis including hot-carrier effect for nanoscale Gate Stack Gate All Around (GASGAA) MOSFETs

The Gate All Around (GAA) MOSFET is considered as one of the most promising devices for downscaling below 50?nm. By surrounding the channel completely, the gate gains increased electrostatic control of the channel and short-channel-effects (SCEs) can be drastically suppressed. However, challenges still remain to resolve the important issues particularly concerning hot-carrier reliability and accurate device models for nanoscale circuit designs. Hot-carrier effects have been the major issues in the long-term stability of subthreshold performances in a nanoscale MOS transistor. In this paper we present a two-dimensional analytical analysis of the subthreshold behavior, subthreshold current and subthreshold swing, including the interfacial hot-carrier effects. The calculated results of the proposed approach match well with those of the 2-D numerical device simulator. The present work provides valuable design insights in the performance of nanoscale CMOS-based devices including hot-carrier degradation effects.     

Insulated gate bipolar transistor (IGBT) modeling using IG-SPICE

A physics-based model for the insulated gate bipolar transistor (IGBT) is implemented into the widely available circuit simulation package IG-SPICE. Based on analytical equations describing the semiconductor-physics, the model accurately describes the nonlinear junction capacitances, moving boundaries, recombination, and carrier scattering, and effectively predicts the device conductivity modulation. In this paper, the procedure used to incorporate the model into IG-SPICE and various methods necessary to ensure convergence are described. The effectiveness of the SPICE-based IGBT model is demonstrated by investigating the static and dynamic current sharing of paralleled IGBTs with different device model parameters. The simulation results are verified by comparison with experimental results     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.     

A 3D analytical modeling of tri-gate tunneling field-effect transistors

In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the tri-gate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson’s equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.     

Compact modeling and simulation of nanoscale fully depleted DG-SOI MOSFETS

A two dimensional analytical model for nanoscale fully depleted double gate SOI MOSFET is presented. Green??s function solution technique is adopted to solve the two dimensional Poisson??s equation using Dirichlet??s and Neumann??s boundary conditions at silicon-silicon di-oxide interface. Based on the derived 2D potential distribution, surface potential distributions in the Si film are analytically obtained. The calculated minimum surface potential is used to develop an analytic threshold voltage model. Simulation is done using ATLAS simulator for a 65?nm device and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data and other published results.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Performance analysis of fully depleted triple material surrounding gate (TMSG) SOI MOSFET

In this paper, analytical model for threshold voltage is derived for fully depleted Triple material Surrounding gate (TMSG) SOI MOSFET. Three gate material of different work functions are introduced in the SOI MOSFET structure to reduce the short channel effects. The two dimensional Poisson equation is solved and based on parabolic approximation method, the model for threshold voltage is developed. The threshold voltage is analyzed for device parameters such as gate length ratios, oxide thickness, silicon thickness, doping concentration. The results of the analytical model values are validated using MEDICI simulation.     

A model for the dc electrical behavior of bulk-barrier diodes

Contents  This paper presents an analytical model for the dc electrical behavior of bulk barrier diodes (BBD's). The proposed model extends previously published models, and includes analytical expressions for all significant quantities of the device dc performance, i.e. barrier height, current density and ideality factor, with respect to the technological parameters and the applied voltage in both bias conditions. The analytical results have been compared with those obtained using the 2-D device simulator S-PISCES, which takes into account the drift–diffusion theory, as well as a concentration and field dependent mobility, the Shockley–Read–Hall and Auger carrier recombination, and the band gab narrowing. Good agreement was obtained between theory and simulation. The device simulation played a very important role in best understanding BBD's behavior, because it could easily take into account parameters strongly affecting the behavior of BBD's, e.g. the free carrier presence in depletion layers, which was very difficult for the analytical model to include. Received: 15 January 2001     

Rotating Heat Exchangers and the Optimization of a Heat Pump

Flow and heat transfer conditions are investigated on rotating flat plates and on blades of tangential blowers. The solution of the three dimensional boundary layer equations for rotating flat plates show that 3-D effects are of influence only in the neighborhood of the axis of rotation. The conditions outside this region can be treated as flow in a 2-D system. The measurements indicate that turbulent flow exists already at Re-values much smaller than Reclit for stationary flat plates. As a result of this, high heat transfer rates can be achieved at lower average velocities. All data taken on rotating flat plates and on the blades of a tangential blower can be correlated by a single dimensionless relationship. The results obtained by theory and measurements are used to derive design curves for the construction of a heat pump. A device built in accordance to these curves performed as predicted. Discussed are also rotating furnaces, radiators and condensers for vapor driven engines.     

Explicit modelling of the double‐gate MOSFET with VHDL‐AMS

This paper presents a new compact model for the undoped, long‐channel double‐gate (DG) MOSFET under symmetrical operation. In particular, we propose a robust algorithm for computing the mobile charge density as an explicit function of the terminal voltages. It allows to greatly reduce the computation time without losing any accuracy. In order to validate the analytical model, we have also developed the 2D simulations of a DG MOSFET structure and performed both static and dynamic electrical simulations of the device. Comparisons with the 2D numerical simulations give evidence for the good behaviour and the accuracy of the model. Finally, we present the VHDL‐AMS code of the DG MOSFET model and related simulation results. Copyright © 2006 John Wiley & Sons, Ltd.     

Analytical modeling of device-circuit interactions for the powerinsulated gate bipolar transistor (IGBT)

The device-circuit interactions of the power insulated gate bipolar transistor (IGBT) for a series resistor-inductor load, both with and without a snubber, are simulated. An analytical model for the transient operation of the IGBT, previously developed, is used in conjunction with the load circuit state equations for the simulations. The simulated results are compared with experimental results for all conditions. Devices with a variety of base lifetimes are studied. For the fastest devices studied (base lifetime=0.3 μs), the voltage overshoot of the series resistor-inductor load circuit approaches the device voltage (500 V) for load inductances greater than 1 μH. For slower devices, though, the voltage overshoot is much less, and a larger inductance can therefore be switched without a snubber circuit (e.g. 80 μH for a 7.1 μs device). The simulations are used to determine the conditions for which the different devices can be switched safely without a snubber protection circuit. Simulations are also used to determine the required values and ratings for protection circuit components when protection circuits are necessary