An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the “virtual cathode” concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si_1?x Ge _x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.     

Comprehensive approach to modeling threshold voltage of nanoscale strained silicon SOI MOSFETs

A comprehensive approach for modeling the threshold voltage of nanoscale strained silicon-on-insulator (SSOI) and strained Si-on-SiGe-on-insulator (SSGOI) MOSFETs is presented. The model includes the effect of strain in terms of Ge mole fraction and various other device parameters—channel length, channel doping, strained silicon film thickness, gate oxide thickness and gate work function. The accuracy of the proposed threshold voltage model is verified using two-dimensional numerical simulations. We have also demonstrated that our model can accurately predict the DIBL effects.     

Modeling the threshold voltage of PNIN SSOI tunnel field‐effect transistor

In this paper, a physically based analytical threshold voltage model for PNIN strained‐silicon‐on‐insulator tunnel field‐effect transistor (PNIN SSOI TFET) is proposed by solving the two‐dimensional (2D) Poisson equation in narrow N⁺ layer and intrinsic region. In the proposed model, the effect of strain (in terms of equivalent Ge mole fraction), narrow N⁺ layer and gate dielectric, and so on, is being considered. The validity of the proposed model is verified by comparing the model results with 2D device simulation results. It is demonstrated that the proposed model can correctly predicts the trends in threshold voltage with varying the device parameters. This proposed model can be effectively used to design, simulate, and fabricate the PNIN SSOI TFETs with the desired performance. Copyright © 2015 John Wiley & Sons, Ltd.     

Performance analysis of fully depleted triple material surrounding gate (TMSG) SOI MOSFET

In this paper, analytical model for threshold voltage is derived for fully depleted Triple material Surrounding gate (TMSG) SOI MOSFET. Three gate material of different work functions are introduced in the SOI MOSFET structure to reduce the short channel effects. The two dimensional Poisson equation is solved and based on parabolic approximation method, the model for threshold voltage is developed. The threshold voltage is analyzed for device parameters such as gate length ratios, oxide thickness, silicon thickness, doping concentration. The results of the analytical model values are validated using MEDICI simulation.     

On the threshold voltage of nanoscale bulk nMOSFETs with [110]/(001) uniaxial stress and quantum effects

Due to the large electron mobility gain cased by uniaxial stress along the [110] directions on (001) silicon substrate, in this paper, the impact of [110]/(001) uniaxial strain and quantum mechanical effects (QMEs) on the threshold voltage of strained-Silicon nMOSFETs is studied by developing a physically-based model. The impact of [110]/(001) stress on the band structure parameters such as density-of-state (DOS) in the conduction and valance band, band-gap and intrinsic carrier concentration is quantized first. Based on a modified threshold surface potential, the threshold voltage model is then proposed by solving the 2-D Poisson’s equation and also by taking short channel effects, quantum effects and other secondary effects into consideration. Our analytical results agree with both TCAD and experimental data. The threshold voltage with the stress along arbitrary orientation can be analyzed analogously. This model can also be used for the design of nanoscale strained-Si nMOSFETs.     

Numerical simulation of electrical characteristics in nanoscale Si/GaAs MOSFETs

In this paper, electrical characteristics of metal-oxide-semiconductor field effect transistor (MOSFET) with silicon/gallium-arsenic (Si/GaAs) stacked film are numerically studied. By calculating several important device characteristics, such as the on-state current, the subthreshold swing, the drain induced barrier lowering, the threshold voltage, the threshold voltage roll-off, and the output resistance, a 50 nm Si/GaAs MOSFET is simulated with respect to different thicknesses of Si/GaAs film. Compared with the results of pure Si MOSFET, Si/GaAs MOSFET shows promising characteristics after properly selecting the thickness of Si/GaAs film. Among Si, germanium (Ge), and Si/Ge MOSFETs, Si/GaAs MOSFET relatively exhibits a higher driving capability due to higher carrier mobility within the Si/GaAs film. However, quantitatively accurate estimation of device characteristics will depend upon more precise calculation of band structure of the stacked film.     

Process modeling of stress and chemical effects in SiGe alloys using kinetic Monte Carlo

In state-of-the-art silicon based process technologies, strained and relaxed SiGe, strained-silicon layers, and process-induced stress are widely present. Based on a literature review, we developed and calibrated continuum and kinetic Monte Carlo process models for chemical and stress effects in SiGe (Zographos et al. in AIP Conf. Proc. 1496:212–216, 2012). In this paper, we explain in full detail the corresponding kinetic Monte Carlo models and calibration. The models take into account the effects on band gap, amorphization, recrystallization, point defect generation and diffusion, extended defect evolution, dopant diffusion and clustering, and dopant segregation. The influence of Ge concentration and strain profile on Si self-interstitials and vacancies properties are deducted from experimental data as well as from ab-initio studies. The {311} interstitial clusters are less stable in the presence of Ge or compressive hydrostatic pressure, and the transformation of {311} defects into dislocation loops is faster. The corresponding parameter adjustments have been calibrated based on experimental data generated within the ATOMICS research project. The effects of Ge and stress on dopant diffusion have been calibrated for boron, arsenic and phosphorus taking into account that in experiments using epitaxial layers of strained SiGe embedded in Si, or strained silicon embedded in relaxed SiGe, boron and phosphorus have been found to segregate at Si/SiGe interfaces.     

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.     

Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs)

In this paper, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs) is presented. The three-dimensional (3D) Poisson equation in cylindrical coordinates has been solved with suitable boundary conditions to find the surface potential along the channel length. The inversion charge density \((Q_{inv} )\) has been calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship. Subsequently, the calculated inversion charge density \((Q_{inv} )\) has been equated to a threshold charge density \((Q_{th})\) in order to find the threshold voltage \((V_{th})\) expression. The effect of physical device parameters, including the tube thickness, on the threshold voltage and drain induced barrier lowering (DIBL) of the device has been discussed. The model results have been verified with the simulation data obtained by the device simulation software ATLAS.     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

Micromechanical optoelectronic switch and amplifier (MIMOSA)

We report for the first time the monolithic integration of a micromechanical modulator and a p-n photodiode on a silicon substrate yielding a versatile optoelectronic device. Because both devices are monolithically integrated on a silicon substrate, the combination is compact with minimal parasitic elements. We demonstrate that such a device combination fields a transistor-like element with positive and negative small-signal voltage amplification. The maximum small-signal voltage gain achieved is 500 while the modulated current of the device exhibits a maximum ON-OFF ratio of 3:1. In addition, while the theoretical current gain of the device is infinite, a 10-pA noise level limited the measured dc current gain to 10⁶     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

Green's function approach for modeling of electrostatic effects in nanoscale fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistors

Exact solution of two‐dimensional (2D) Poisson's equation for fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistor is derived using three‐zone Green's function solution technique. Framework consists of consideration of source–drain junction curvature. 2D potential profile obtained forms the basis for estimation of threshold voltage. Temperature dependence of front surface potential distribution, back surface potential distribution and front‐gate threshold voltage are modeled using temperature sensitive parameters. Applying newly developed model, surface potential and threshold voltage sensitivities to gate oxide thickness have been comprehensively investigated. Device simulation is performed using ATLAS 2D (SILVACO, 4701 Patrick Henry Drive, Bldg. Santa Clara, CA 95054 USA) device simulator, and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data. Copyright © 2013 John Wiley & Sons, Ltd.     

Self-Consistent Subband Structure and Mobility of Two Dimensional Holes in Strained SiGe MOSFETs

The motivation to research strained SiGe layers on relaxed silicon is to enhance the very low hole mobility observed in conventional Si MOSFETs. This is mainly due to large hole effective masses and strong surface roughness scattering. In this work, the buried SiGe quantum well, chosen as the active channel for carrier transport, enhances mobility in two ways. First, the carriers are confined in the SiGe well and are removed from the Si-SiO₂ interface, so interface roughness is not a big factor. Secondly, strained SiGe has a lower hole effective mass than unstrained Si and the mobility is expected to increase as the Ge concentration increases. We present the results of a self-consistent subband structure and low field mobility calculations for holes in a Si-SiGe heterostructure FET. Our results are in agreement with the experimental work by Garone and coworkers, indicating the validity of our model.     

Reliability of SiGe HBTs for Power Amplifiers—Part II: Underlying Physics and Damage Modeling

This paper presents the underlying physics and modeling of aggressively biased cascode SiGe heterojunction bipolar transistor power amplifier (PA) cores under large-signal operating conditions. The damage characteristics observed during RF operation, particularly the base leakage and collector-base (CB) junction failure, are investigated in detail using dc stress methods. Base leakage was characterized across geometry, voltage, and current conditions, and a damage model is purposed based on Shockley–Read–Hall theory and the reaction–diffusion equation. This model is used to predict damage under aggressive RF operations, in order to extract the operational lifetime of SiGe PAs. The onset of CB junction failure was modeled using the current-gain collapse model, and it accurately captures the failure threshold current $I_{rm Fail}$ observed during RF stress.      

新型SiGe开关功率二极管的特性分析

提出了一种新型SiGe/Si异质结P－i-N开关功率二极管结构，在分析器件结构机理的基础上，用Medici模拟了该器件的特性。结果表明，该功率二极管具有低的正向压降，较少的存贮电荷，其性能远远超过Si的同类型结构。     

Electronic structure and transmission characteristics of SiGe nanowires

Atomistic disorder such as alloy disorder, surface roughness and inhomogeneous strain are known to influence electronic structure and charge transport. Scaling of device dimensions to the nanometer regime enhances the effects of disorder on device characteristics and the need for atomistic modeling arises. In this work SiGe alloy nanowires are studied from two different points of view: (1) Electronic structure where the bandstructure of a nanowire is obtained by projecting out small cell bands from a supercell eigenspectrum and (2) Transport where the transmission coefficient through the nanowire is computed using an atomistic wave function approach. The nearest neighbor sp³d⁵s^* semi-empirical tight-binding model is employed for both electronic structure and transport. The connection between dispersions and transmission coefficients of SiGe random alloy nanowires of different sizes is highlighted. Localization is observed in thin disordered wires and a transition to bulk-like behavior is observed with increasing wire diameter.