Random Telegraph Noise in 30 nm FETs with Conventional and High-κ Dielectrics

The magnitude of fractional current variation in ultra-small (30 nm channel length) MOSFETs due to single charge trapping-detrapping events at any position within the gate dielectric is studied using numerical simulation. These random telegraph signals in the drain current indicate the amplitude of low frequency MOSFET noise. Simulations are performed for realistic devices with poly-silicon gates subject to poly-silicon depletion, and for both SiO₂ and HfO₂ as dielectric materials.     

Accurate modeling of Metal/HfO<Subscript>2</Subscript>/Si capacitors

In this work, we study the differences caused in the Capacitance-Voltage (C-V) characteristics of MOS devices when SiO₂ is replaced by HfO₂ as the gate dielectric. A self-consistent Schrödinger-Poisson solver has been developed to include the effects of quantum confinement and the influence of different parameters such as the effective mass, barrier height, and dielectric constant (κ) of the gate insulator material. Two different devices are considered: A Double Gate MOSFET and a Surrounding Gate Transistor. The validity of the Equivalent Oxide Thickness (EOT) is studied.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Preparation of hafnium oxide thin films by sol–gel method

Hafnium oxide (HfO₂) films were grown on SiO₂/Si substrates by a sol–gel method, and their crystalline structure, microstructure and electrical properties were investigated. X-ray diffraction analysis indicated that the monoclinic HfO₂ films could be obtained by annealing at 500 °C. A transmission electron microscopy (TEM) image showed that the films were grown as a spherulite grain structure with a mean grain size of approximately 15 nm. The dielectric constant of the HfO₂ films of 300 nm was approximately 21.6, and the current–voltage measurements showed that the leakage current density of the HfO₂ films was approximately 1.14?×?10^?5 A/cm² at an applied electric field of 100 kV/cm. The sol–gel method-fabricated HfO₂ films are concluded to be feasible for MEMS applications, such as capacitive-type MEMS switches.     

Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO2/Si Gate Structure

Ferroelectric gate FET's with BLT/HfO₂ structure were fabricated on 5-inch-scale Si wafer using well-refined CMOS compatible 0.8 μm-based fabrication processes for the first time. We obtained excellent device characteristics and good memory operations of the fabricated n-ch and p-ch MFIS-FET's, in which the memory window and on/off drain current ratio of typical p-ch memory device were measured to be 1.5 V at V_G of ±5 V and 8 orders-of-magnitude, respectively. We also confirmed by evaluating the gate voltage and gate size dependences of device properties that the fabricated devices showed quantitatively reasonable ferroelectric memory operations.     

A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

Simulations of Scaled Sub-100 nm Strained Si/SiGe p-Channel MOSFETs

This paper investigates scaled sub-100 nm strained Si channel p-type MOSFETs. For a 30–40% Ge content SiGe buffer, 1D Poisson-Schrödinger analysis indicates that the parasitic effects of the SiGe buffer are negligible in small devices with high n-type channel doping (>10¹⁷ cm^?3). The device published by IBM and calibrated by us has been scaled down to a 35 nm physical gate length and shows notable performance enhancement over the Si control MOSFET. Well-tempered MOSFET designs have also been adopted to study potential performance improvement associated with the introduction of a strained Si channel. These provide a performance improvement comparable with the scaled versions of the IBM devices for effective gate length down to 25 nm. Improved well engineering is required to suppress short channel effects during the scaling process.     

Growth and characterization of UHV sputtering HfO2 film by plasma oxidation and low temperature annealing

Ultra-thin (∼4.0 nm) HfO₂ films were fabricated by plasma oxidation of sputtered metallic Hf films with post low temperature annealing. Advantage of this fabrication process is that the pre-deposition of Hf metal can suppress the formation of interfacial layer between HfO₂ film and Si substrate. The as-deposited HfO₂ films were subsequently treated by rapid thermal annealing at different temperatures in N₂ to investigate the effects of thermal annealing on the physical and electrical properties of HfO₂ film. A SiO₂-rich interface layer was observed after higher temperature rapid thermal annealing and the phase change of HfO₂ film from amorphous into crystalline occurred at about 700^∘C. As a result of higher temperature annealing, effective dielectric constant and leakage current were significantly influenced by the formation of interface layer and the crystallization of HfO₂ film.     

碳化硅器件的短路保护：设计准则和电路

为了保障碳化硅(silicon carbide,Si C)在发生短路故障时可安全可靠的关断,需在掌握其短路特性基本规律的前提下,针对Si C短路耐受时间较短、短路下器件漏源极电压拐点不明显等特征,展开去饱和保护电路(desaturation fault protection,DESAT)电路中关键参数的研究,并制定其工程化设计的参考标准。在此基础上,文中进一步提出基于氮化镓(galliumnitride,GaN)的高速、低传输延时的DESAT短路保护电路,短路保护电路的驱动动作延时仅为常规基于硅器件DESAT电路的23.2%。所提出的氮化镓DESAT电路为SiC MOSFET短路保护电路的更优越的实现方案。     

Electrical properties of ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructures

Ultrathin HfO₂ gate dielectrics have been deposited on strained Si_0.69Ge_0.3C_0.01 layers by rf magnetron sputtering. The polycrystalline HfO₂ film with a physical thickness of ∼6.5 nm and an amorphous interfacial layer with a physical thickness of ∼2.5 nm have been observed by high resolution transmission electron microscopy (HRTEM). The electrical properties have been studied using metal-oxide-semiconductor (MOS) structures. The fabricated MOS capacitors on Si_0.69 Ge_0.3C_0.01 show an equivalent oxide thickness (EOT) of 2.9 nm, with a low leakage current density of ∼4.5 × 10 ^{− 7} A/cm² at a gate voltage of –1.0 V. The fixed oxide charge and interface state densities are calculated to be 1.9 × 10¹² cm^{− 2} and 3.3 × 10 ¹¹ cm^{− 2}eV⁻¹, respectively. The temperature dependent gate leakage characteristics has been studied to establish the current transport mechanism in high-k HfO₂ gate dielectric to be Poole–Frenkel one. An improvement in electrical properties of HfO₂ gate dielectrics has been observed after post deposition annealing in O₂ and N₂ environments.     

选择区域外延槽栅结构GaN常关型MOSFET的研究

高性能GaN常关型功率开关器件的实现是目前研究的热点。槽栅结构GaN常关型MOSFET以其栅压摆幅冗余度大、栅极漏电流小等优势受到广泛关注。制备槽栅结构GaN常关型MOSFET需要的刻蚀方法会在栅极沟道引入缺陷,影响器件的稳定性。首先,提出选择区域外延方法制备槽栅结构GaN常关型MOSFET,期望避免刻蚀对栅极沟道的损伤;再通过改进选择区域外延工艺(包括二次生长界面和异质结构界面的分离及抑制背景施主杂质),使得二次生长的异质结构质量达到标准异质结构水平。研究结果表明,选择区域外延方法能够有效保护栅极导通界面,使器件具备优越的阈值电压稳定性;同时也证明了选择区域外延方法制备槽栅结构GaN常关型MOSFET的可行性与优越性。     

Can the Density Gradient Approach Describe the Source-Drain Tunnelling in Decanano Double-Gate MOSFETs?

As MOSFETs are scaled into the deep sub-micron (decanano) regime, quantum mechanical confinement and tunnelling start to dramatically affect their characteristics. It has already been demonstrated that the density gradient approach can be successfully calibrated in respect of vertical quantum confinement at the Si/SiO₂ interface and can reproduce accurately the quantum mechanical threshold voltage shift. In this paper we investigate the extent to which the density gradient approach can reproduce direct source-drain tunnelling in short double gate MOSFET devices.     

Use of WKB approximation for analytical boundary conditions in numerical solution of Schrödinger equation: application to semiconductor–high‐k dielectric interfaces

Numerical methods used to solve 1D Schrödinger's equation in quantum structures, such as Numerov's integration of wavefunction or the shooting method iterative solution of energy levels, require knowledge of two‐point boundary conditions at interfaces. This is especially true when the interfaces are not symmetrical or where exponential decay of wavefunction at asymptotically large distances does not hold. A closed‐form expression for boundary conditions, which is not sensitive to intermediate solutions at interfaces, can minimize possible divergence during iterations and relax simulation grid size and simulation time. In this work, the Wentzel‐Kramers‐Brillouin (WKB) approximation within potential barriers is proposed to analytically calculate the boundary conditions for abrupt interfaces, such as dielectric–semiconductor interface. An analytical expression for the slope at the interface is derived, and the errors are estimated with respect to numerical methods. An application is shown for self‐consistent solution of coupled Poisson–Schrödinger's equations at multi‐layer HfO₂‐SiO₂ dielectric gate stack corresponding to International Technology Roadmap for Semiconductors‐projected 10 nm bulk single‐gate Complementary Metal‐Oxide‐Semiconductor (CMOS) technology node, where wavefunction penetration into the dielectric is of critical importance. Application to dual gate structures with 5 nm fin width and high‐k dielectric with 0.5 nm equivalent oxide thickness is also shown. A quantum mechanical simulator ‘hksim’ based on this principle is posted for public domain usage. Copyright © 2015 John Wiley & Sons, Ltd.     

Underlying design advantages for GaN MOSFETs compared with GaN HFETs for power applications

This study investigates the underlying reasons and quantifies the advantages the GaN MOSFET has over the GaN HFET for high voltage and power applications. Calibrated simulations with equivalent material model files show that equivalent dimensioned devices are capable of producing similar on-state modes of operation, and achieve similar effective mobility at equivalent larger electric fields. However, during sub-threshold operation, the GaN MOSFET is shown to contain a much lower carrier concentration than the GaN HFET. This prolongs the breakdown avalanche effect in the GaN MOSFET (3500 V) by roughly five times larger than the GaN HFET (600 V) for devices of similar dimensions. Implementing the MOS structure can potentially resolve fundamental constraints for high voltage power applications caused by current device architects.     

第三代半导体GaN功率开关器件的发展现状及面临的挑战

氮化镓(GaN)材料具有优异的物理特性,非常适合于制作高温、高速和大功率电子器件,具有十分广阔的市场前景。Si衬底上GaN基功率开关器件是目前的主流技术路线,其中结型栅结构(p型栅)和共源共栅级联结构(Cascode)的常关型器件已经逐步实现产业化,并在通用电源及光伏逆变等领域得到应用。但是鉴于以上两种器件结构存在的缺点,业界更加期待能更充分发挥GaN性能的"真"常关MOSFET器件。而GaN MOSFET器件的全面实用化,仍然面临着在材料外延方面和器件稳定性方面的挑战。     

Analysis of tunneling currents in multilayer black phosphorous and $$\hbox {MoS}_{2}$$ non-volatile flash memory cells

This paper presents a theoretical study of tunneling current density and the leakage current through multi-layer (stacked) trapping layer in the gate dielectric in MOS non-volatile memory devices. Two different 2D materials (\(\hbox {MoS}_{2}\) and black phosphorous) with a combination of high-k dielectric (\(\hbox {HfO}_{2}\)) have been used for the study with differently ordered stacks i.e., as trapping layer and substrate. The material properties of 2D materials like density of states, effective mass and band structure has been evaluated using density functional theory simulations. Using the Maxwell–Garnett effective medium theory we have calculated the effective barrier height, effective bandgap, effective dielectric constant and effective mass of the gate dielectric stacks. By applying WKB approximation in the multi-layer trapping layer we have studied the effect of the direct and Fowler–Nordheim tunneling currents. The leakage current in all the different stack combinations used has also been evaluated. The results obtained have shown to match the required dynamics of a memory device.     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.     

Advanced Power Module Packaging and Integration Structures for High Frequency Power Conversion:From Silicon to GaN

The emerging of commercial high-voltage gallium nitride(GaN) power devices provides extraordinary switching performance over silicone devices, which enables high-voltage power conversion switching at megahertz range.Such outstanding features also pose strong challenges for device packaging design since the package parasitics can significantly influence the device switching characteristics, and thus can shadow the advantages brought by GaN devices. Designers have been dealing with these challenges brought by high du/dt and high-frequency switching operation even since the silicon(Si) era when fast switching Si MOSFET is first developed and came up with lots of inspiring advanced power module packaging structures to mitigate the problems.This paper presents a review of advanced power module packaging and integration structures that are suitable for high frequency power conversion.The review covers the heritage from the high frequency Si MOSFET packaging to the state-of-the-art for GaN devices.