A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS

A low‐power low‐jitter voltage‐mode (VM) transmitter with two‐tap pre‐emphasis and impedance calibration for high‐speed serial links is presented. Based on a comprehensive analysis of the relationship between impedance, supply current, and pre‐emphasis of the output driver, an impedance control circuit (ICU) is presented to maintain the 50 Ω output impedance and suppress the reflection, a self‐biased regulator is proposed to regulate the power supply, and an edge driver is introduced to speed up the signal transition time. Therefore, the signal integrity (SI) of the transmitter is improved with low power consumption. The whole transmitter is implemented in 65‐nm CMOS technology. It provides an eye height greater than 688 mV at the far end with a root‐mean‐squared jitter of less than 6.99 ps at 5 Gbps. The transmitter consumes 15.2 mA and occupies only 370 μm × 230 μm. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Crosstalk cancelling voltage‐mode driver for multi‐Gbps parallel DRAM interface

For multi‐Gb/s/pin parallel dynamic random access memory (DRAM) interface, a crosstalk cancelling voltage‐mode driver is proposed. The voltage‐mode driver is composed of a main driver and sub‐drivers where the cancellation signal is generated by the sub‐drivers. The outputs of the main driver and sub‐drivers are combined by a capacitive coupling so the direct current (DC) output swing is not affected by the crosstalk cancellation and the sub‐drivers may not consume DC power. The proposed crosstalk cancelling voltage‐mode driver implemented in a 0.11‐µm complementary metal‐oxide semiconductor (CMOS) technology improves the horizontal eye openings by 22.6 ps at 4‐Gbps/pin. Copyright © 2014 John Wiley & Sons, Ltd.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

Current‐fed isolated PFC pre‐regulator for multiple LED lamps with extended lifetime

To emit high‐quality LED light, one or a bin of LED lamp(s) is normally driven by a PWM‐controlled constant current source to minimize device variation and achieve accurate brightness control. Powered from offline AC mains, the front‐end power converters should provide a relatively low DC voltage bus for the inputs of post‐end LED current regulators. To match the long lifetime of LEDs, the whole LED driver (ballast) should work as durably as the LEDs. However, the lifetime of the driver is usually limited by the high‐voltage electrolytic charge storage capacitors used in conventional PFC pre‐regulators. In this paper, our previously proposed resonant current‐fed isolated PFC pre‐regulator is extended to operate in discontinuous conduction mode (DCM). It allows the use of the low‐voltage storage capacitors on the transformer secondary, and therefore extends the overall lifetime of the LED lighting system. A detailed procedure for finding the expected lifetime of the low‐voltage electrolytic capacitor is given. As before, the high‐voltage stress on the main switches, which is typical in current‐fed isolated converters, is reduced substantially by taking advantage of the transformer leakage inductance necessary for resonance. Additionally, high efficiency is ensured by the use of dual non‐cascading structures. Steady‐state state‐space averaging analysis is performed for designing the converter in DCM operation. A prototype converter is built to verify performance of the proposed PFC LED pre‐regulator. Copyright © 2011 John Wiley & Sons, Ltd.     

Low energy/delay overhead level shifter for wide‐range voltage conversion

Multi‐supply voltage systems on chip have been widely explored for energy‐efficient elaborations. A main challenge of multi‐supply voltage designs is the interfacing of digital signals coming from ultra‐low‐voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay‐efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single‐stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull‐up network on the basis of the occurring transition. A test chip was fabricated in 180 nm complementary metal–oxide–semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100 mV of input voltages to 1.8 V, while assuring an average propagation delay of about 26 ns, an average static power of 100 pW, and an energy per transition of 140 fJ for the target voltage‐level conversion from 0.4 to 1.8 V. Copyright © 2016 John Wiley & Sons, Ltd.     

Study and implementation of a 15‐W driver for piezoelectric actuators

This paper studies and implements a 15‐W driver for piezoelectric actuators. The discussed driver is mainly composed of a flyback converter and a power operational amplifier (P‐OPA). The flyback converter produces a variable DC voltage to supply the P‐OPA, which outputs an amplified sinusoidal signal with a DC bias of 100 V to drive the piezoelectric actuator. The power losses can be reduced because the supply voltage of the P‐OPA varies with the peak of the input signal. The power conversion efficiency of the driver can thus be promoted up to more than 30%. From the experimental results, the implemented prototype possesses some advantageous features, such as a nearly constant output‐to‐input voltage gain, a high slew rate, a high input impedance, a low output impedance, and low output voltage ripples. Copyright © 2016 John Wiley & Sons, Ltd.     

An amplifier‐offset‐insensitive and high PSRR subthreshold CMOS voltage reference

An amplifier‐offset‐insensitive complementary metal‐oxide‐semiconductor (MOS) voltage reference (CVR) circuit with high power supply ripple rejection (PSRR) is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed CVR circuit can suppress the direct current offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions and improving the PSRR are presented. The proposed CVR circuit is implemented in a standard 0.18 μm complementary MOS process. Measured results show that the reference can run with down‐to 0.9 V supply voltage, while the power consumption is only 70 nW. The measured PSRR is better than ?37 dB over the full frequency range.     

A universal‐input high‐power‐factor power supply without electrolytic capacitor for multiple lighting LED lamps

The AC–DC power supply for LED lighting application requires a long lifetime while maintaining high‐efficiency, high power factor and low cost. However, a typical design uses electrolytic capacitor as storage capacitor, which is not only bulky but also with short life span, thus hampering performance improvement of the entire LED lighting system. In this article, a SEPIC‐derived power factor correction topology is proposed as the first stage for driving multiple lighting LED lamps. Along with a relatively large voltage ripple allowable in a two‐stage design, the proposal of LED lamp driver is able to eliminate the electrolytic capacitor while maintaining high power factor and high efficiency. To further increase the efficiency of LED driver, we introduced and used the twin‐bus buck converter as the second‐stage current regulator with Pulse Width Modulation (PWM) dimming function. The basic operating principle and the deign consideration are discussed in detail. A 50‐W prototype has been built and tested to verify the proposal. Copyright © 2011 John Wiley & Sons, Ltd.     

Single‐stage single‐switch PFC converter for wide‐input extreme step‐down voltage applications

This paper presents a new single‐stage single‐switch high power factor correction AC/DC converter suitable for low‐power applications (< 150 W) with a universal input voltage range (90–265 V_rms). The proposed topology integrates a buck–boost input current shaper followed by a buck and a buck–boost converter, respectively. As a result, the proposed converter can operate with larger duty cycles compared with the existing single‐stage single‐switch topologies, hence, making them suitable for extreme step‐down voltage conversion applications. Several desirable features are gained when the three integrated converter cells operate in discontinuous conduction mode. These features include low semiconductor voltage stress, zero‐current switch at turn‐on, and simple control with a fast well‐regulated output voltage. A detailed circuit analysis is performed to derive the design equations. The theoretical analysis and effectiveness of the proposed approach are confirmed by experimental results obtained from a 100‐W/24‐V_dc laboratory prototype. Copyright © 2011 John Wiley & Sons, Ltd.     

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre‐charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre‐charged to full V_DD. Read port is designed such that for the read ‘1’ operation, BL shares its charge with BLB, and for read ‘0’ operation, BL is charged toward V_DD and BLB is discharged to the ground. The proposed non‐V_DD BL pre‐charging and the charge‐sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting pre‐amplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single‐ended write driver is also presented that only conditionally charges the write BL. The proposed 10‐transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six‐transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

Two novel low power and very high speed pulse triggered flip‐flops

Two novel low power and high‐speed pulse triggered flip‐flops were presented in this paper. Short circuit current was controlled, and race condition between pull‐up and pull‐down branches was removed, which caused reduction of power consumption. On the other hand, the number of stack transistors in the discharging path was reduced which decreased delay of the flip‐flops. The first proposed flip‐flop reduced the number of transistors and the second proposed flip‐flop used conditional data mapping and removed floating node of the first flip‐flop. Post‐layout simulation result showed that the first proposed flip‐flop reduced 21% of power delay product and the second proposed flip‐flop reduced 16% of power delay product in comparison with other flip‐flops in 50% of data switching activities. Copyright © 2014 John Wiley & Sons, Ltd.     

A 1.2 V 83 dB DR single‐ended input SC ΔΣ modulator including a large‐swing analog buffer for portable ECG applications

This study proposes a subsystem consisting of an analog buffer and a single‐ended input to a fully differential ΔΣ modulator to obtain low‐power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low‐power consumption is achieved. The ΔΣ modulator with a second order, 1 bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non‐inverting path implement a single‐ended input to fully‐differential signals. A double sampling technique is proposed for a digital‐to‐analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low‐power consumption. Input‐bias and output‐bias transistors working in the weak‐inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2 V, signal bandwidth of 250 Hz, and sampling frequency of 128 kHz, the measurement results show that the modulator with a buffer achieves a 77 dB peak signal‐to‐noise‐distortion ratio, an effective‐number‐of‐bits of 12.5 bits, an 83 dB dynamic range, and a figure‐of‐merit of 156 dB. The total chip size is approximately 0.28 mm² with a standard 0.13 µm Complementary Metal‐Oxide‐Silicon (CMOS) process. Copyright © 2016 John Wiley & Sons, Ltd.     

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

We present a low‐supply voltage (2V) low‐power consumption (500W) analogue phase‐locked loop (PLL), working at two low frequencies (1 and 10kHz), to be used in an integrated lock‐in amplifier. An externally settable control bit allows the switching operation between the two different frequencies. The circuit has been designed in a standard 0.6–m CMOS technology and differs from the standard analogue PLL architectures for the current mode implementation of both the loop filter and of the oscillator. Three different locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull‐in ranges are about ±250Hz around 1 and ±1.3kHz around 10kHz, with pull‐in times of about 10 and 4ms, respectively. Copyright © 2003 John Wiley & Sons, Ltd.     

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The duplex current‐reused topology with equivalent three common‐source gain stages cascaded is utilized to fulfil the low‐power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk‐bias control is employed to improve the linearity performance with large‐signal swing and to extend the auxiliary transistors bias‐control range. The proposed LNA is fabricated in a 0.18‐um 1P5M complementary metal–oxide–semiconductor process and consumes a 3.13‐mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of −19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

Proposal of Series‐Parallel Continuously Regulated Chopper Suitable for Auxiliary Power Supply of Railway Vehicle

The conventional auxiliary power supply (APS) of a railway vehicle is directly connected to the catenary through the LC filter. Hence, the switching devices of the APS must have a high breakdown voltage to account for catenary voltage fluctuation. On the other hand, low‐voltage switching devices have better characteristics that are desirable for low‐loss and high‐frequency operation. Therefore, a step‐down converter is incorporated between the LC filter and inverter to adapt to catenary voltage fluctuations when using low‐voltage switching devices. This paper proposes the series‐parallel continuously regulated chopper as a novel step‐down converter. First, the fundamental operation characteristics and output voltage control method of the proposed chopper are introduced. The simulation and experimental results for the fundamental characteristics are then described; the simulation and experimental values were almost the same as the theoretical values. The proposed chopper controls the output voltage at the expected value without dramatic fluctuation regardless of the input voltage fluctuation. In addition, a resonance damping control for a constant power load is proposed. The operational characteristics were considered under different potential distributions or load conditions.     

A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity

We present the design of a nanopower sub‐threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 µm CMOS technology. The circuit provides a temperature‐compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start‐up circuit. Copyright © 2013 John Wiley & Sons, Ltd.     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.