Multiplier‐less VLSI architectures for radix‐22 folded pipelined complex FFT core

The advantages of a multiplier‐less architecture are reduction in hardware and latency. This paper proposes multiplier‐less architectures for the implementation of radix‐2² folded pipelined complex FFT core based on coordinate rotation digital computer (CORDIC) and new distributed arithmetic (NEDA). The number of points considered in the work is sixteen and the folding is done by a factor of four. The proposed designs have been implemented on Xilinx XC5VSX240T‐2FF1738 FPGA and also have been synthesized using the Synopsys design compiler. Proposed designs based on NEDA have reduced area over 83% and based on CORDIC have a reduced area over 78%. The observed slice‐delay product for NEDA based designs are 2.196 and 5.735, and for CORDIC based design is 2.369. Copyright © 2014 John Wiley & Sons, Ltd.     

An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

The conventional magnetic tunneling junction (MTJ)‐based non‐volatile D flip‐flop (NVDFF) has a slow D‐Q delay and a tradeoff between its D‐Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ‐based non‐volatile semidynamic flip‐flop (NVSDFF) has a semidynamic structure that ensures a fast D‐Q delay and separates the sensing circuit from the D‐Q signal path to reduce the sensing current without affecting the D‐Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry‐compatible 45 nm model parameter show that the D‐Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller. Copyright © 2012 John Wiley & Sons, Ltd.     

Robust wide‐area damping controller design for inter‐area oscillations with signals' delay

A new wide‐area damping control strategy is investigated for flexible AC transmission systems (FACTS) device using wide‐area measurement system (WAMS) signals. The purpose is to design a dynamic output wide‐area damping controller (WADC) for improving the stability of interconnected power systems. The time‐varying delay of wide‐area signal is incorporated into the design process, which can effectively reduce the delay effect on the damping performance. First, a discrete‐time plant model with time‐varying delay is established for power systems; then by using the proposed improved free‐weighting matrices (IFWMs) approach and a convex optimization algorithm, a new and less conservative delay‐dependent stability criterion, expressed in the terms of linear matrix inequalities (LMIs), is obtained without ignoring any useful terms on the difference of a Lyapunov function. Detailed case studies on a 4‐machine two‐area benchmark test system and 16‐machine five‐area NETS‐NYPS interconnected system show that the designed WADC can not only maintain effective damping performance under the condition of time‐varying delay but also get the maximum wide‐area time delay. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design of a reversible structure for memory in quantum-dot cellular automata

Complementary metal oxide semiconductor (CMOS) technology has limitations in reducing the area and size of circuits. The disadvantages of this technology include high power consumption and temperature problems. Quantum-dot cellular automata (QCA) is a new technology that can overcome these shortcomings. Reversible logic is technology used to reduce the power loss in QCA. QCA can be used to design memories that require high operating speed. In this paper, we propose a structure for the reversible memory in QCA. The proposed structure utilizes three-layer technology, which has a significant impact on circuit size reduction. The proposed structure for the reversible memory has 63% improvement in cell number, a 75% improvement in area occupancy, and a 60% reduction in delay compared to the previous best structure.     

A time‐delay technique to improve GBW on negative feedback amplifiers

This paper presents a new method to improve the GBW (gain‐bandwidth product) on negative feedback amplifiers. The proposed method is based on the introduction of time‐delay elements in the feedback loop, which can be exploited to retrieve significant bandwidth enhancements. This delayed feedback concept is analyzed, and considerations are presented for first‐order amplifiers, based on theoretical analysis. The concept is simulated and further demonstrated in a practical example using a series‐shunt feedback amplifier with a TL081 operational amplifier (OA) and a 36‐m‐long coaxial cable as a delay element. Measured experimental results show a maximum bandwidth improvement of almost 90%, from a theoretical maximum of 141%. Copyright © 2007 John Wiley & Sons, Ltd.     

Dynamic mixed serial–parallel content addressable memory (DMSP CAM)

A novel dynamic mixed serial–parallel content addressable memory (DMSP CAM) is proposed to achieve both low‐power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45‐nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy‐delay product reduction compared with the other serial–parallel mixed CAMs. Copyright © 2011 John Wiley & Sons, Ltd.     

基于分块转置的二维快速傅里叶变换的FPGA设计

离散二维快速傅里叶变换被广泛应用于数字图像处理，对工程领域具有重要意义。通常2D FFT使用行列分解计算，即先沿着行计算一维快速傅里叶变换，再沿列计算。由于现场可编程门阵列的数据传输带宽以及相关存储硬件的物理结构特性的限制，该方案不满足高分辨图像实时处理的需求。采用行FFT 转置 行FFT的方案，虽减少计算过程中直接内存访问控制器的等待时间且能提高2D FFT的计算效率，但目前矩阵转置实现有很大的局限性。传统的设计使用加载和存储指令来完成矩阵的换位。提出一种基于快速分块转置的2D FFT方案，通过搭建转置模块与四路并行1D FFT模块，充分利用FPGA片上资源以降低延时。实验基于Xilinx Kintex UltraScale FPGA，在相同的时钟频率以及并行条件下，对比不同的2D FFT计算方案。在实验误差范围内，本文提出的解决方案使计算效率提升约15倍。     

Efficient memory architecture for image processing

This Letter presents a novel purpose‐designed architecture to realize efficient dual‐port memory structures for image processing applications. The main innovation proposed here is the exploitation of single‐port (SP) sub‐banks to achieve the same data bandwidth offered by a true dual‐port (TDP) memory, but significantly reducing the access time and resources requirement. When compared with a conventional TDP memory bank, the proposed strategy requires up to 25% less silicon area and consumes up to 9% lower power. It also exhibits an access time up to 15% lower. When used within an Actel FPGA RTAX device to realize an image compressor based on the 2D DWT and the SPIHT algorithm, the memory structure proposed here allows reaching an 11 Mpixels/s frame‐rate, which is 77% higher than that achieved by simply instantiating the SP memory banks available on chip. Copyright © 2010 John Wiley & Sons, Ltd.     

Efficient optimization‐oriented design methodology of high‐order 3‐D filters using 2‐D and 3‐D electromagnetic simulators

This paper proposes a computationally highly efficient interface between two‐dimensional (2‐D) and three‐dimensional (3‐D) electromagnetic (EM) simulators for the optimization‐oriented design of high‐order 3‐D filters. In a first step, the novel optimization‐oriented design methodology aligns the 3‐D EM simulator response with the 2‐D EM simulator response of a low‐order 3‐D filter by using an inverse linear space mapping optimization technique. Then, a second mapping performs a calibration with the optimal 2‐D and 3‐D design parameters obtained from the first mapping. The optimization of high‐order filters is carried out using only the efficient 2‐D EM simulator, and the calibration equations directly give the design parameters of the 3‐D filter. The potential and the effectiveness of the proposed optimization‐oriented design methodology are demonstrated through the design of C‐band 3‐D evanescent rectangular waveguide bandpass filters with increasing orders from three to eight. Copyright © 2014 John Wiley & Sons, Ltd.     

Design space exploration for sparse matrix‐matrix multiplication on FPGAs

The design and implementation of a sparse matrix‐matrix multiplication architecture on field‐programmable gate arrays is presented. Performance of the design, in terms of computational latency, as well as the associated power‐delay and energy‐delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user‐tunable power‐delay and energy‐delay tradeoffs by employing different number of processing elements (PEs) in the architecture design and different block size in the blocking decomposition. Such ability allows designers to employ different on‐chip computational architecture for different system power‐delay and energy‐delay requirements. It is in contrast to conventional dense matrix‐matrix multiplication architectures that always favor the maximum number of PEs and largest block size. In our implementation, the better energy consumption and power‐delay product favors less PEs and smaller block size for the 90%‐sparsity matrix‐matrix multiplications. Although in order to achieve better energy‐delay product, more PEs and larger block size are preferred. Copyright © 2011 John Wiley & Sons, Ltd.     

Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

High‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.     

Low‐cost multi‐standard simultaneous forward and inverse video transform core

This paper presents a cost‐effective, two‐dimensional (2‐D) discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) capable of MPEG1/2/4, H.264 4 × 4/8 × 8, and VC‐1 4 × 4/8 × 8/4 × 8/8 × 4 standards. We developed multilevel factor sharing in conjunction with distributed arithmetic in a scheme referred to as common sharing distributed arithmetic to enable sharing of the coefficient matrix circuit and replace multipliers with adders and shifters. By taking advantage of the similarities between DCT and IDCT transforms, we were able to implement an interlaced sorting method in a single circuit of the DCT and IDCT transform core in order to reduce area overhead while enabling the simultaneous operation of DCT and IDCT. The proposed design arranges the data of the first dimension and second dimension in order to reuse the same 1‐D core to compute 2‐D data. In this manner, first dimension and second dimension data of DCT and IDCT can be processed simultaneously in a single transform core. The efficacy of the proposed approach has been verified by fabricating a test chip using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm complementary metal‐oxide semiconductor process. The inverse transform core was shown to have an operating frequency of 227 MHz and throughput of 454 Mpel/s with a gate count of 32.5 k. Copyright © 2015 John Wiley & Sons, Ltd.     

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.     

Active fault‐tolerant control for switched systems with time delay

This paper focuses on the problem of active fault‐tolerant control for switched systems with time delay. By utilizing the fault diagnosis observer, an adaptive fault estimate algorithm is proposed, which can estimate the fault signal fast and exactly. Meanwhile, a delay‐dependent criterion is obtained with the purpose of reducing the conservatism of the adaptive observer design. Based on the fault estimation information, an observer‐based fault‐tolerant controller is designed to guarantee the stability of the closed‐loop system. In terms of linear matrix inequality, sufficient conditions are derived for the existence of the adaptive observer and fault‐tolerant controller. Finally, a numerical example is included to illustrate the efficiency of the proposed approach. Copyright © 2011 John Wiley & Sons, Ltd.     

基于FPGA的回波模拟器设计与实现

回波模拟器主要完成对雷达引信机射频信号的延迟和衰减,并传输至接收端.传统的模拟延时和模拟衰减通常采用多路开关控制延迟线的方法实现,由于模拟电路存在温度漂移、器件老化影响、抗干扰性能差等缺点,从而使得输入信号质量下降,线路越长,噪声的积累也就越多.以现场可编程门阵列Vertex-5系列的FPGA为核心,研究了数字化回波模拟器总体设计方案,综合利用了模数转换、数字下变频DDC、数字延迟衰减等技术,实现了雷达引信机射频信号的延迟衰减精确可调,完成了频率、功率信号的实时测量,简化了回波模拟器硬件结构,提高了系统集成度和可靠性.     

Rejection of narrow‐band disturbances subject to uncertain time delays

In this work, the problem of designing feedback contollers for the rejection of narrow‐band disturbances is considered. The design technique proposed herein is based on the overparametrization of a nominal minimum‐variance controller, which is designed by means of an ARMA model of a sinusoid in noise. The extra degrees of freedom so introduced are used to improve the robustness of the nominal controller, when the time delay of the plant is subject to uncertainties, by minimizing a minimum‐variance performance index along a one‐dimensional line. Copyright © 2000 John Wiley & Sons, Ltd.     

Gramian‐based model order reduction of parameterized time‐delay systems

Time‐delay systems (TDSs) frequently arise in circuit simulation especially in high‐frequency applications. Model order reduction (MOR) techniques can be used to facilitate the simulation of TDSs. On the other hand, many kinds of variations, such as temperature and geometric uncertainties, can have significant impact on the transient responses of TDSs. Therefore, it is important to preserve parametric dependence during the MOR procedure. This paper presents a new parameterized MOR scheme for TDSs with parameter variations. We derive parameterized reduced‐order models (ROMs) for TDSs using balanced truncation by approximating the Gramians in the multi‐dimensional space of parameters. The resulting ROMs can preserve the parametric dependence, making it efficient for repeated simulations under different parameter settings. Numerical examples are presented to verify the accuracy and efficiency of our proposed algorithm. Copyright © 2012 John Wiley & Sons, Ltd.     

Two novel low power and very high speed pulse triggered flip‐flops

Two novel low power and high‐speed pulse triggered flip‐flops were presented in this paper. Short circuit current was controlled, and race condition between pull‐up and pull‐down branches was removed, which caused reduction of power consumption. On the other hand, the number of stack transistors in the discharging path was reduced which decreased delay of the flip‐flops. The first proposed flip‐flop reduced the number of transistors and the second proposed flip‐flop used conditional data mapping and removed floating node of the first flip‐flop. Post‐layout simulation result showed that the first proposed flip‐flop reduced 21% of power delay product and the second proposed flip‐flop reduced 16% of power delay product in comparison with other flip‐flops in 50% of data switching activities. Copyright © 2014 John Wiley & Sons, Ltd.     

Low power Wallace multiplier design based on wide counters

Multiplication is one of the most basic arithmetic operations. It is used in digital applications, central processing units, and digital signal processors. In most systems, the multiplier lies within the critical path and hence, due to probability and reliability issues, the power consumption of the multiplier has become very important. Moreover, as chips shrink and their power densities increase, power is becoming a major concern for chip designers. The ever increasing demand for portable applications with their limited battery lifetime indicates that power considerations should be a center stone in today's designs and the future's designs. Thus, all this has motivated us to provide a novel circuit design technique for a low power multiplier without compromising the multiplier's speed. This paper presents a new power aware multiplier design based on Wallace tree structure. A new algorithm is proposed using high‐order counters to meet the power constraints imposed by mobility and shrinking technology. Commonly used multipliers of widths 8, 16, and 32 bits are designed based on the proposed algorithm. The new approach has succeeded in reducing the total number of gates used in the multiplier tree. Simulations on Altera's Quartus‐II FPGA simulator showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multiplier's size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power‐delay product in 32‐bit multipliers. Copyright © 2011 John Wiley & Sons, Ltd.