A technique for the design of microprocessor memory systems

A systematic technique for the design of the chip select logic for microprocessor memory systems is given. In this technique, a memory table must be completed that shows the logic levels on each address line required to place every device (RAM, ROM, and I/O ports) at their desired locations in memory space. The memory table helps a designer visualize the system requirements and properly design the address decoding logic. The possibilities of bus contention can easily he recognized and avoided either by hardware or use of proper device locations in software. The technique is also a useful analysis tool     

Efficient memory architecture for image processing

This Letter presents a novel purpose‐designed architecture to realize efficient dual‐port memory structures for image processing applications. The main innovation proposed here is the exploitation of single‐port (SP) sub‐banks to achieve the same data bandwidth offered by a true dual‐port (TDP) memory, but significantly reducing the access time and resources requirement. When compared with a conventional TDP memory bank, the proposed strategy requires up to 25% less silicon area and consumes up to 9% lower power. It also exhibits an access time up to 15% lower. When used within an Actel FPGA RTAX device to realize an image compressor based on the 2D DWT and the SPIHT algorithm, the memory structure proposed here allows reaching an 11 Mpixels/s frame‐rate, which is 77% higher than that achieved by simply instantiating the SP memory banks available on chip. Copyright © 2010 John Wiley & Sons, Ltd.     

A forward‐only recursion algorithm for MAP decoding of linear block codes

The evolution of digital mobile communications along with the increase of integrated circuit complexity has resulted in frequent use of error control coding to protect information against transmission errors. Soft decision decoding offers better error performance compared to hard decision decoding but on the expense of decoding complexity. The maximum a posteriori (MAP) decoder is a decoding algorithm which processes soft information and aims at minimizing bit error probability. In this paper, a matrix approach is presented which analytically describes MAP decoding of linear block codes in an original domain and a corresponding spectral domain. The trellis‐based decoding approach belongs to the class of forward‐only recursion algorithms. It is applicable to high rate block codes with a moderate number of parity bits and allows a simple implementation in the spectral domain in terms of storage requirements and computational complexity. Especially, the required storage space can be significantly reduced compared to conventional BCJR‐based decoding algorithms. Copyright © 2002 John Wiley & Sons, Ltd.     

New designs of low/high‐pass and mid‐pass/stop FIR digital filters

New designs of highly efficient low/high‐ and mid‐pass/stop (centre‐symmetric band‐pass/stop) FIR non‐recursive digital filters are presented. The designs are based on the modulation property of DFT, applied to the already presented MAXFLAT halfband low‐pass filters. The presented filters have explicit formulas for their tap‐coefficients, and therefore are very easy to design. They have highly smooth frequency response and wider transition regions like MAXFLAT filters. The design formulae are modified to give new classes of low/high‐ and mid‐pass/stop filters, for which, like in equiripple filters, the transition bandwidth can be reduced by increasing the size of ripple on magnitude response. It is shown, with the help of design examples, that the performance of these filters is comparable to that of equiripple filters. Copyright © 2001 John Wiley & Sons, Ltd.     

Workstation clusters for parallel computing

Workstation clusters have become an increasingly popular alternative to traditional parallel supercomputers for many workloads requiring high performance computing. The use of parallel computing for scientific simulations has increased tremendously in the last ten years, and parallel implementations of scientific simulation codes are now in widespread use. There are two dominant parallel hardware/software architectures in use today: distributed memory, and shared memory. Systems implementing shared memory provide cooperating processes with a shared memory address space that can be accessed by all processors. In shared memory systems, parallel processing occurs through the use of shared data structures, or through emulation of message passing semantics in software. Distributed memory systems are composed of a number of interconnected computational nodes, which do not share memory, but can communicate with each other through a high-performance network of some kind. Parallelism is achieved on distributed memory systems with multiple copies of the parallel program running on different nodes, sending messages to each other to coordinate computations. The messages used in a distributed memory parallel program typically contain application data, synchronization information, and other data that controls the execution of the parallel program     

Design of a contention‐free parallel double‐flow MAP decoder

Parallel processing and double‐flow methods, which are used to increase the speed of turbo‐code decoding, cause memory contentions. Although memory contentions due to parallel processing can be resolved by adopting the quadratic polynomial permutation (QPP) interleaver, the double‐flow method still causes memory contentions because of its read/write sequences from both ends of the input packets. Thus, we propose a modified architecture to resolve memory contentions for the double‐flow method to fit the QPP interleaver. In our experiment, the proposed method has a shorter decoding time and smaller hardware size compared the conventional method. A bit‐accurate simulation was performed, and hardware implementation with field‐programmable gate arrays (FPGAs) led to a high throughput of 80 Mbps. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Implementation of vibration suppression control on FWL processor

In motion or process control systems, a variety of design techniques have been proposed because of the demand for high performance. The higher performance we demand, the higher the degree of the controller becomes. The controller is generally designed by a CAD system and implemented with a microprocessor. But the microprocessor does not have enough precision to realize the results of design by the CAD system. Therefore, the system performance is degraded by finite word length (FWL) effects. To deal with FWL problems, many design methods have been considered in the signal processing field, and high‐ordered digital filters are often used. Among these methods, the implementation technique based on the state‐space realization can minimize the sensitivity to perturbation of coefficients. Noting that optimal realizations with the same transfer function are unique only up to an orthogonal similarity transformation, we must choose the realization within this class of optimal realizations. In this paper, we present an algorithm to find a state‐space realization which minimizes the frequency‐weighted sensitivity measure of the controller performance. Furthermore, we present some experimental results to verify the effectiveness of the proposed algorithm. © 1999 Scripta Technica, Electr Eng Jpn, 128(1): 45–52, 1999     

Turbo码译码器的DSP实现

Turbo码以其优越的性能在通信系统中越来越受到人们的重视.由于Turbo码译码算法的复杂性,译码器通常需占用大量的存储空间和较长的运算时间,难以满足实际系统的要求.本文在深入研究Max-Log-MAP译码算法的基础上,对该算法进行了合理优化,提出了一种基于DSP的高效的软件实现方法.基于此方法实现的Turbo码译码器具有较低的误码率和较小的译码时延,在语音通信和数据通信中具有广泛的应用前景.     

Harmonic spectrum analysis of the output voltage and grid‐side filter design for three‐level voltage‐source converters

Because of the complex arithmetic computation of the traditional three‐level space vector modulation (SVM), its hardware implementation is difficult to achieve. Moreover, the normal approach of acquiring the output voltage harmonic is sensitive to the simulation step, measurement accuracy, system noise, etc. This paper proposes a new method for analyzing the voltage harmonic spectrum of the three‐level converter. Furthermore, the minimum value of the inductance of the grid‐side filters is designed on this basis. First, the formulas of the duty cycle and the modulation waveform of the three‐level SVM algorithm are easily derived using some simple linear calculations under the 120° coordinate. Then, considering the characteristics of the digital circuits, the harmonic components of the output voltage are calculated using Fourier analysis. Third, a precise analytical design of the minimum inductance value of grid‐connected converters with LCL and L input filters is presented. Finally, the validity of this approach is verified by using experimental results. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Discrete time filters for doubly stochastic poisson processes and other exponential noise models

The well‐known Kalman filter is the optimal filter for a linear Gaussian state‐space model. Furthermore, the Kalman filter is one of the few known finite‐dimensional filters. In search of other discrete‐time finite‐dimensional filters, this paper derives filters for general linear exponential state‐space models, of which the Kalman filter is a special case. One particularly interesting model for which a finite‐dimensional filter is found to exist is a doubly stochastic discrete‐time Poisson process whose rate evolves as the square of the state of a linear Gaussian dynamical system. Such a model has wide applications in communications systems and queueing theory. Another filter, also with applications in communications systems, is derived for estimating the arrival times of a Poisson process based on negative exponentially delayed observations. Copyright © 1999 John Wiley & Sons, Ltd.     

Bandwidth extension,linearity enhancement,and cost reduction techniques for continuous‐time channel‐select filters

Achieving a wide bandwidth in a conventional active‐RC filter requires large power consumption and is often accompanied by significant performance degradation. In this paper, a new structure to implement active‐RC continuous‐time filters and also a new frequency compensation scheme for the operational amplifiers that are the main building blocks of active‐RC filters are proposed. Exploiting these techniques increases the maximum possible bandwidth with lower power consumption in comparison with the conventional architectures, reduces die area, and enhances the dynamic range. The effectiveness of these methods has been verified by analysis and simulation of the conventional and proposed filters under identical conditions. Both the analytical investigations and extensive simulation results prove that the adopted techniques improve the performance of continuous‐time filters considerably in terms of bandwidth and linearity while reducing the die area. Simulations have been carried out in a standard 90‐nm CMOS process by using Advanced Design System (ADS), and the proposed filter features 11.08‐dB spurious‐free dynamic range improvement and 5.9 times bandwidth enhancement. Also, the total on‐chip capacitance is made 2.4 times smaller by using the new biquad structure. Copyright © 2016 John Wiley & Sons, Ltd.     

Area-Power Efficient VLSI Implementation of Multichannel DWT for Data Compression in Implantable Neuroprosthetics

Time-frequency domain signal processing of neural recordings, from high-density microelectrode arrays implanted in the cortex, is highly desired to ease the bandwidth bottleneck associated with data transfer to extra-cranial processing units. Because of its energy compactness features, discrete wavelet transform (DWT) has been shown to provide efficient data compression for neural records without compromising the information content. This paper describes an area-power minimized hardware implementation of the lifting scheme for multilevel, multichannel DWT with quantized filter coefficients and integer computation. Performance tradeoffs and key design decisions for implantable neuroprosthetics are presented. A 32-channel 4-level version of the circuit has been custom designed in 0.18-mum CMOS and occupies only 0.22 mm² area and consumes 76 muW of power, making it highly suitable for implantable neural interface applications requiring wireless data transfer.     

Adaptation of turbo coding and equalization in turbo equalization for time-varying and frequency-selective channels

A number of authors have sought to combine equalization and decoding in an iterative system in order to reduce the effects of frequency and temporal dispersiveness of time-varying frequency-selective channels. In the recent literature, several architectures based on these iterative systems have been proposed. One can note architectures which combine a maximum a posteriori (MAP) equalizer and decoder, architectures formed by an interference canceller and MAP decoder, architectures implementing a decision feedback equalizer and a MAP decoder, etc. Most of these architectures require accurate channel estimation to adapt the equalizer filters or to execute the MAP equalizers. This article presents a turbo equalizer architecture for time-varying frequency-selective channels without channel estimators. The proposed turbo equalizer consists of an interference canceller in direct-adaptation mode and a turbo decoder. In order to reduce noise correlation, the addition of a transverse filter to the interference-canceller architecture is proposed. The reliability factor for variable time-varying frequency-selective channels is also redefined in order to improve the performance of the turbo decoder. The architecture of the proposed turbo equalizer reduces considerably the effects of frequency and temporal dispersiveness of time-varying frequency-selective channels depending on the normalized Doppler frequency range.     

Interlaced switch boxes placement for three‐dimensional FPGA architecture design

Three‐dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wire‐length reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two‐dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18‐µm CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM‐based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay‐power product improvement and 43% area‐delay product reduction. Copyright © 2010 John Wiley & Sons, Ltd.     

High-quality low-complexity wavelet-based compression algorithm for audio signals

Wavelets have recently emerged as a powerful tool for signal compression, particularly in the areas of image, video, and audio compression. In this paper, we present a low-complexity wavelet-based audio compression algorithm that is capable of handling fairly arbitrary audio sources. The algorithm transforms the incoming audio data into the wavelet domain, and compresses data by exploring redundancy in the wavelet coefficients and exploiting the large runs of zeros in the transformed signal. Also there is a possibility of applying a threshold to the non-zero coefficients, thus a further increase in the number of zeros is expected. The audio signal is first preprocessed to scale down the wavelet coefficients. Then the preprocessed signal is wavelet transformed using a bi-orthogonal discrete wavelet transform (DWT) and threshold by applying energy compaction strategy. Encoding represents the threshold coefficients in compact form. A new encoding technique that is easy to implement, and that provides a reasonable compression ratio for a certain acceptable distortion level has been developed to encode the threshold DWT. So, a bit rate can be controlled such that the algorithm operates at virtually any pre-selected bit rate. The motivation of using the bi-orthogonal wavelet transform is that it permits the use of a much broader class of filters, and this class includes symmetric linear phase filters. The superior performance of this algorithm is also demonstrated by comparing it with two other popular audio compression techniques and this meets the requirements of multimedia computing.     

A class of digitally programmable nth‐order filters

A family of new high‐order filters capable of providing all filter functions without changing the circuit topology is proposed for integrated circuit applications. The proposed filters are based on simple active elements, namely, digitally controlled current amplifiers (DCCAs) and unity gain voltage buffers (VBs). Gains of DCCAs are digitally programmed to adjust the coefficients of transfer functions. R2R ladders are also utilized to increase the tuning flexibility of the proposed filters. A filter replicating the famous KHN biquad is extended to realize general nth‐order filters. Comparison with the recent works shows that the proposed approach results in more efficient realizations compared with its counterparts based on other current‐mode active elements. Experimental results obtained from a fourth‐order filter implemented using devices fabricated in a 0.35‐µm CMOS process are provided. Copyright © 2011 John Wiley & Sons, Ltd.     

FPGA‐based implementation for improved control scheme of grid‐connected PV system with 3‐phase 3‐level NPC‐VSI

The large scale penetration of renewable energy resources has boosted the need of using improved control technique and modular power electronic converter structures for efficient and reliable operation of grid‐connected systems. This study investigates the performance of a grid‐connected 3‐phase 3‐level neutral‐point clamped voltage source inverter for renewable energy integration by using improved current control technique. For medium or high‐voltage grid interfacing, the multilevel inverter structure is generally used to reduce the voltage stress across the switching device as well as the harmonic distortion. The neutral‐point clamped voltage source inverter is controlled by using decoupling technique along with the proper grid synchronization via moving average filter–based phase‐locked loop. The moving average filter–based phase‐locked loop is used to reduce the delay in grid angle estimation under balanced as well as distorted grid conditions. A Lyapunov‐based approach for analysing the stability of the system has also been discussed. In this study, the hardware‐in‐loop (HIL) simulation of the control algorithm and the grid synchronization technique is realized using Virtex‐6 FPGA ML605 evaluation kit. The performance of the system is analyzed by conducting a time‐domain simulation in the Matlab/Simulink platform and its performance is examined in the HIL environment. The simulation and the hardware cosimulation results are presented to validate the effectiveness of the proposed control scheme.     

IC‐constrained optimization of continuous‐time Gm–C filters

This paper presents an automated synthesis procedure for integrated continuous‐time fully‐differential G_m?C filters. Such procedure builds up on a general extended state‐space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB^® framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright © 2010 John Wiley & Sons, Ltd.     

A new course on supercomputers and parallel architectures

Parallel processing and distributed computing are two areas attracting a great deal of attention. Several universities and institutions are involved in the teaching of courses on parallel programming, distributed operating systems and parallel algorithms, but very few of them offer a course from the hardware point of view. The course structure presented in this paper gives a considerable emphasis on the hardware for parallel processing. Various topics such as the design of high speed computing devices, hardware design of multiple pipelines, design of a variety of memory configurations, design of an NXN interconnection network and the hardware for systolic architectures and neural network architectures are presented in this course. Students have the opportunity to actually design a distributed shared memory system using IBM PC machines and write software for them. The assignments for the course are in the form of both individual and group projects on the implementation of various schemes for parallel processing such as synchronization mechanisms (e.g., locks and barrier) in hardware. In addition, a group project deals with the design of a pipelined floating point unit. Further, a complementary course on VLSI provides the necessary skills for the students to implement the devices as a VLSI chip. Students also have the opportunity to do hands on work with transputers and develop hardware and software based around them. This course has received good feedback both from academia and industries within Australia     

Phase‐Locked Loop Using Complex‐Coefficient Filters for Grid‐Connected Inverter

Recently, photovoltaic (PV) power systems have attracted considerable attention in attempts to mitigate global warming. In a PV power system, it is necessary to synchronize the grid voltage when a PV inverter is interconnected with a grid. This paper proposes a high‐speed and high‐precision phase‐locked loop (PLL) using complex‐coefficient filters for a single‐phase grid‐connected inverter. The proposed PLL can detect the phase of grid voltage that has superimposed harmonic components for grid fault. Moreover, numerical results show the effectiveness of the proposed method.