一种面向可重构硬件的编译中间表示方法

中间表示氓是构建编译和高级综合工具的基础。本文设计了一种面向可重构硬件的编译中间表示方法。这一工作是我们设计的高级综合工具的一部分。实验结果表明,应用这 一中间表示,可以将C源程序高效地映射到目标可重构硬件上。     

面向应用的可重构编译器ASCRA(英文)

在很多应用领域已经开展了可重构计算的研究,但是由于缺乏高层设计工具,设计者需要较深的软件和硬件专业知识才能开发GPP/RAU架构的程序,阻碍了其大规模应用。提出了一种面向应用的可重构编译器——ASCRA的初始架构,它可以自动将C语言映射为VHDL语言,从而解决可重构计算中自动编译工具的瓶颈。ASCRA编译器主要研究软硬件划分技术和面向硬件的优化技术,如脉动阵列、循环流水技术。在ML505开发平台上,设计实现了ASCRA编译器的验证平台,并通过实验给出了核心程序段生成VHDL代码的综合信息。     

可重构资源管理及硬件任务布局的算法研究

可重构系统具有微处理器的灵活性和接近于ASIC的计算速度,可重构硬件的动态部分重构能力能够实现计算和重构操作的重叠,使系统能够动态地改变运行任务,可重构资源管理和硬件任务布局方法是提高可重构系统性能的关键.提出了基于任务上边界计算最大空闲矩形的算法(TT-KAMER),能够有效地管理系统的空闲可重构资源;在此基础上使用FF和启发式BF算法进行硬件任务的布局.实验表明,算法能够有效地实现在线资源分配与任务布局,获得较高的资源利用率.     

一种基于传输触发体系结构的可重构Hash函数处理器：TTAH

Hash函数是密码学中保证数据完整性的有效手段,性能需求使得某些应用必须采用硬件实现。本文通过分析常用Hash函数在算法上的相似性设计出了专用可重构单元,并将这些可重构单元耦合到传输触发体系结构中,得到一种可重构Hash函数处理器TTAH。常用Hash算法在TTAH上的映射结果表明：与细粒度可重构结构相比,其速度快,资源利用率高;与ASIC相比,可以在额外开销增加较小的前提下有效地支持多种常用Hash函数。     

面向轻量级分组密码的高性能可重构架构

针对目前采用专用集成电路的硬件实现架构难以满足不同应用对灵活性需求的问题,提出一种面向轻量级分组密码的高性能可重构架构(HRALBC).通过分析42种主流的轻量级分组密码算法,提取出算法的模式特征和组合特征;以模式特征结果和组合特征结果为依据设计出可重构处理单元;根据算法映射规律设计可重构处理单元阵列,进而进行架构整体...     

可重构嵌入式数控系统的研究

提出了一种可重构的嵌入式数控系统，通过与安装有网格中间件和网格支持工具的上位机相连，可以很方便地作为制造网格的一个可重构节点。在硬件设计上，主控系统、插补和补偿模块以及伺服模块通过CAN总线互连，实现嵌入式数控系统硬件的可重构性。在软件设计上，采用软件芯片的思想，同时设计数控软件自动生成系统，实现了软件的可重构性。     

可重构系统中硬件任务布局布线算法研究

可重构计算系统中,二维可重构硬件任务的布局布线问题是影响系统资源利用率的重要因素。在异质化的可重构器件和任务模型基础上,对可重构硬件任务进行了适当分类,并提出一种能够对多类型可重构硬件任务同时布局布线的算法DRS-TCW。实验表明,该算法能够有效提高可重构器件的资源利用率和任务布线连通率。     

星载可重构计算机硬件验证平台设计

随着片上系统SoPC设计技术与大规模可编程逻辑器件的发展，嵌入式处理器在可编程器件上的实现得到了广泛的应用。介绍了一款基于VirtexⅡ XC2V3000的星载可重构计算机硬件验证平台的设计。在介绍该处理器内部结构的基础上，详细给出了硬件原理图和PCB布局布线的设计，并且阐述了硬件平台搭建完成后的测试和验证的步骤。此设计对于类似的嵌入式处理器的硬件设计具有一定的借鉴作用。     

二通道重构算法研究与实现

基于传统的多通道采样技术,以二通道为例,对二通道采样和信号重构算法进行了分析,对传统理论算法进行了改进和提高,通过信号重构算法,实现了宽带信号的高速高精度采样,计算机仿真结果表明,改进后的二通道采样及重构方法可有效地减小频谱失真,实现信号的高精度采样和实时重构。同时,本文给出了基于美国德州仪器公司(TI公司)最新的高速DSP芯片DM8168的硬件系统,从硬件上实现了本文所提出的二通道重构算法。     

基于动态可重构FPGA的自演化硬件概述

演化硬件研究如何利用遗传算法进行硬件自动设计,或者设计随外界环境变化而自适应地改变自身结构的硬件,在电子设计自动化、自主移动机器人控制器、无线传感器网络节点等领域都有潜在的应用价值. 自演化硬件是在硬件内部完成遗传操作和适应度计算,利用支持动态部分可重构的FPGA芯片上的微处理器核实现遗传算法,模拟生物群体演化过程搜索可能的电路设计并配置片上的可重构逻辑,找到最优或较优的设计结果,从而实现自适应硬件. 当电路发生故障时,自演化硬件自动搜索新的配置,利用片上冗余资源取代故障区域,从而实现自修复硬件. 介绍了基于动态部分可重构FPGA的自演化硬件的基本思想、体系结构以及研究现状,总结并提出了亟待解决的关键技术,指出高效的电路染色体编码表示与可重构逻辑配置位串之间的映射方式是当前研究的重点之一.     

Techniques for improving the security and manageability of IPsec policy

We discuss the strengths and weaknesses of existing tools with respect to the Internet Protocol security (IPsec) name mapping problem: how to ensure a correct mapping between application-layer target names and network-layer target names. We show that DNSSEC is neither necessary nor sufficient for solving the IPsec name mapping problem. We describe design and implementation results for new techniques that are applicable to legacy applications to partially or completely solve the IPsec name mapping problem. As a corollary, we obtain programming recommendations that make it easier to apply these techniques. We show how the set of current IPsec policy parameters can usefully be expanded. We give a prototype of a modified lookup API and argue that the modified API is the preferred long-term solution to the IPsec name mapping problem. We also cover the implications for IPsec key management. Finally, we summarize the environments where IPsec is being used today and discuss which IPsec name mapping techniques are most appropriate for these environments.     

Automatic Generation of UML Class Diagrams for Object-oriented Design and Programing Course

UML Class diagram generation from textual requirements is an important task in object-oriented design and programing course. This study proposes a method for automatically generating class diagrams from Chinese textual requirements on the basis of Natural Language Processing (NLP) and mapping rules for sentence pattern matching. First, classes are identified through entity recognition rules and candidate class pruning rules using NLP from requirements. Second, class attributes and relationships between classes are extracted using mapping rules for sentence pattern matching on the basis of NLP. Third, we developed an assistant tool integrated into a precision micro classroom system for automatic generation of class diagram, to effectively assist the teaching of object-oriented design and programing course. Results are evaluated with precision, accuracy and recall from eight requirements of object-oriented design and programing course using truth values created by teachers. Our research should benefit beginners of object-oriented design and programing course, who may be students or software developers. It helps them to create correct domain models represented in the UML class diagram.     

Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus

The reliability of FPGA based hardware designs has become an important field of research particularly for space computing. Traditionally, redundancy is utilized in FPGA based designs to achieve reliable or error-tolerant computing. However, the redundant designs vary according to the granularity level and the voter placement algorithms used for the hardware design. The resulting circuit configurations vary in area, latency and power as well as in the achieved reliability. While the evaluation of area, latency and power is done by the FPGA design tools, quantitative data for reliability are usually not derived. Consequently, there is a need for an automated reliability evaluation tool especially considering the huge design space of redundant circuit structures. In this paper, we combine the Boolean difference error calculator (BDEC), a probabilistic reliability model for hardware designs, with a reliability model for fault-tolerant circuit structures. As a result, we are able to study the reliability of fault-tolerant circuit structures at the logic layer. We focus on fault-tolerant circuits to be implemented in FPGAs and show how to extend our combined model from combinational to sequential circuits. For an automated analysis, we develop a MATLAB-based tool utilizing our extended BDEC model. With this tool, we conduct a case study on dynamic reliability management and show how quantitative reliability data obtained from this tool improves the four-dimensional Pareto optimization for area, latency, power and reliability.     

Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits

This paper presents a physical mapping tool for quantum circuits, which generates the optimal universal logic block (ULB) that can, on average, perform any logical fault-tolerant (FT) quantum operations with the minimum latency. The operation scheduling, placement, and qubit routing problems tackled by the quantum physical mapper are highly dependent on one another. More precisely, the scheduling solution affects the quality of the achievable placement solution due to resource pressures that may be created as a result of operation scheduling, whereas the operation placement and qubit routing solutions influence the scheduling solution due to resulting distances between predecessor and current operations, which in turn determines routing latencies. The proposed flow for the quantum physical mapper captures these dependencies by applying (1) a loose scheduling step, which transforms an initial quantum data flow graph into one that explicitly captures the no-cloning theorem of the quantum computing and then performs instruction scheduling based on a modified force-directed scheduling approach to minimize the resource contention and quantum circuit latency, (2) a placement step, which uses timing-driven instruction placement to minimize the approximate routing latencies while making iterative calls to the aforesaid force-directed scheduler to correct scheduling levels of quantum operations as needed, and (3) a routing step that finds dynamic values of routing latencies for the qubits. In addition to the quantum physical mapper, an approach is presented to determine the single best ULB size for a target quantum circuit by examining the latency of different FT quantum operations mapped onto different ULB sizes and using information about the occurrence frequency of operations on critical paths of the target quantum algorithm to weigh these latencies. Experimental results show an average latency reduction of about 40 % compared to previous work.     

Mapping and hierarchical self-organizing neural networks for VLSIplacement

We have developed mapping and hierarchical self-organizing neural networks for placement of very large scale integrated (VLST) circuits. In this paper, we introduce MHSO and MHSO2 as two versions of mapping and hierarchical self-organizing network (MHSO) algorithms. By using the MHSO, each module in the placement wins the competition with a probability density function that is defined according to different design styles, e.g., the gate arrays and standard cell circuits. The relation between a placement carrier and movable modules is met by the algorithm's ability to map an input space (somatosensory source) into an output space where the circuit modules are located, MHSO2 is designed for macro cell circuits. In this algorithm, the shape and dimension of each module is simultaneously considered together with the wire length by a hierarchical order. In comparison with other conventional placement approaches, the MHSO algorithms have shown their distinct advantages. The results for benchmark circuits so far obtained are quite comparable to simulated annealing (SA), but the computation time is about eight-ten times faster than with SA.     

Easing semantically enriched information retrieval—An interactive semi-automatic annotation system for medical documents

Mapping medical concepts from a terminology system to the concepts in the narrative text of a medical document is necessary to provide semantically accurate information for further processing steps. The MetaMap Transfer (MMTx) program is a semantic annotation system that generates a rough mapping of concepts from the Unified Medical Language System (UMLS) Metathesaurus to free medical text, but this mapping still contains erroneous and ambiguous bits of information. Since manually correcting the mapping is an extremely cumbersome and time-consuming task, we have developed the MapFace editor.The editor provides a convenient way of navigating the annotated information gained from the MMTx output, and enables users to correct this information on both a conceptual and a syntactical level, and thus it greatly facilitates the handling of the MMTx program. Additionally, the editor provides enhanced visualization features to support the correct interpretation of medical concepts within the text. We paid special attention to ensure that the MapFace editor is an intuitive and convenient tool to work with. Therefore, we recently conducted a usability study in order to create a well founded background serving as a starting point for further improvement of the editor's usability.     

Quantifying the impact of uncertainty in embedded systems mapping for NoC based architectures

We describe a modeling framework to capture and account for uncertainty in design parameters in embedded systems. We then develop an uncertainty-aware solution to the problem of mapping in embedded systems that uses Network-on-Chip (NoC) based architecture platforms. The problem of mapping is formulated as a multi-objective - reliability, performance, and energy consumption - optimization problem. To solve this problem, we propose a solution based on the NSGA-II genetic algorithm and Monte Carlo simulation techniques. The solution is implemented as a computer-aid design tool that can generate robust 3D Pareto frontiers in the solution space formed by the design objectives of reliability, performance, and energy consumption. Comparison to several state-of-the-art models and solutions for the mapping problem, indicate that significant differences in the actual values of the design attribute of interest exist when one considers uncertainty in design parameters. For example, in the case of mapping with reliability as the only objective, 10% uncertainty in design parameters can lead to a 10.06% difference in MTTF estimation. In the case of mapping with execution time and energy consumption as objectives, the difference in 2D Pareto frontiers due to 10% uncertainty in design parameters can be up to 7.9%. These differences are important because they can mislead the overall optimization process of mapping toward suboptimal solution points. The DESUU-NOC tool that implements the proposed multi-objective mapping algorithm has as a main feature and contribution of this paper the ability to generate 3D Pareto frontiers comprised of robust solution points.     

Developing platform specific model for MPSoC architecture from UML-based embedded software models

In this paper, we describe a technique to design UML-based software models for MPSoC architecture, which focuses on the development of the platform specific model of embedded software. To develop the platform specific model, we define a process for the design of UML-based software model and suggest an algorithm with precise actions to map the model to MPSoC architecture. In order to support our design process, we implemented our approach in an integrated tool. Using the tool, we applied our design technique to a target system. We believe that our technique provides several benefits such as improving parallelism of tasks and fast-and-valid mapping of software models to hardware architecture.     

A programmable array processor architecture for flexible approximate string matching algorithms

Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don’t care, complement and classes symbols. We also simulate and evaluate the proposed architecture on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 8–340 times faster execution than a desktop computer with a Pentium 4 3.5 GHz for all algorithms when the length of the pattern is 1024.     

On the relational representation of complex specialization structures

The mapping of entity-relationship schemas (ER schemas) that contain complex specialization structures into the relational model requires the use of specific strategies to avoid inconsistent states in the final relational database. In this paper, we show that for this mapping to be correct it is required to enforce a special kind of integrity constraint, the key pairing constraint (KPC). We present a mapping strategy that use simple inclusion dependencies to enforce KPC and show that this strategy can be used to correctly map specialization structures that are more general than the simple specialization structures considered by previous strategies.