微机管理信息系统的升级

越来越多的管理信息系统转向先进的Ｏｌｉｅｎｔ／Ｓｅｒｖｅｒ体系结构，实践证明，由于有ＯＤＢＣ技术的强有力支持以及ＦＣＢ功能完善的窗口，Ｆｏｘｐｒｏ平台升级到Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ体系结构是技术可行的，资金方面也是小企业可以承担的。     

Client/Server环境下ODBC的发展

数据库的研究和应用是当今计算机最活跃的领域之一，但是各种数据库产品之间存在许多差异。开放数据库互连（ＯＤＢＣ）为应用程序独立于数据库产品，提高程序可移植性提供了新的途径。本文主要描述了在Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ环境下，ＯＤＢＣ体系结构的发展     

基于Telnet协议和Clinet／Manager／Server结构综合的信息检索…

本文提出了综合Ｔｅｌｎｅｔ协议和Ｃｌｉｅｎｔ／Ｍａｎａｇｅｒ／Ｓｅｒｖｅｒ结构的网络服务模型；在基于Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ结构的ＲＤＢＭＳＳＹＢＡＳＥ基础上实现了Ｔｅｎｅｔ协议和Ｃｌｉｅｎｔ／ｍａｎａｇｅｒ／Ｓｅｒｖｅｒ结构综合的图书馆信息检索应用系统，构造了图书馆网络信息服务系统的Ｃｌｉｅｎｔ／Ｍａｎａｇｅｒ／Ｓｅｒｖｅｒ．     

利用PB对ORACLE数据库的应用开发

本文介绍了一个基于Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ模型下的管理查询系统的设计与实现．同时给出了在ＷｉｎｄｏｗｓＮＴＳｅｒｖｅｒ及Ｗｉｎｄｏｗｓ９５操作系统下配置ＯＲＡＣＬＥ７．３３数据库及ＰＢ的ＯＤＢＣ接口的方法,并介绍了使用ＰｏｗｅｒＢｕｉｌｄｅｒ５．０对系统开发的一些技巧．     

基于SQL Server的应用程序的优化

本文简单介绍了ＳＱＬＳｅｒｖｅｒ系统优化技术,并根据实际经验,讨论了一些影响ＳＱＬＳｅｒｖｅｒ数据库内部影响ＳＱＬＳｅｒｖｅｒ应用程序性能的因素以及解决方案。一般的Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ应用程序通常都采用ＯＤＢＣ方式访ＩＮＳＱＬＳｅｒｖｅｒ数据库,这样会影响ＳＱＬＳｅｒｖｅｒ应用程序的性能。在Ｄｅｌｐｈｉ中,采用ＢＤＥ（ＢｏｒｌａｎｄＤａｔａｂａｓｅＥｎｇｉｎｅ）,应用程序不经过ＯＤＢＣ就可以访问数据库,可以在一定的程度上提高ＳＱＬＳｅｒｖｅｒ应用程序的性能。经过开发实践表明：要提高应用程序…     

用FoxPro for Windows实现Client／Server

“Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ”已在计算机业界形成了一种潮流。本文在讨论Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ计算模式和特点的基础上，介绍Ｍｉｃｒｏｓｏｆｔ公司为Ｗｉｎｄｏｗｓ平台提出的ＯＤＢＣ技术，并阐述了在Ｆｏｘｐｒｏｆｏｒ Ｗｉｎｄｏｗ环境下实现Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ计算模式的技术。     

可互操作的对象数据库FIODB的体系结构

对异构数据源的数据共享和数据源间的互操作是ＣＩＭＳ，ＣＡＳＥ等工程领域急待解决的问题，本文介绍了可互操作的面向对象数据库ＦＩＯＢＤ的基于Ｃｌｉｅｎｔ的多Ｓｅｒｖｅｒ体系结构及主要技术。     

一个基于NOVELL／ORACLE的Client／Server计算环境系统平台

信息系统平台的建设是信息系统建设的前提和基础，直接影响着信息系统作用的发挥。本文围绕着代表９０年代网络技术发展水平的Ｃｌｉｅｎｔ．Ｓｅｒｖｅｒ热点技术，介绍了基于Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ体系结构的系统平台模式的特征，并以合肥市税务局信息系统平台建设为背景，描述了一个基于ＮＯＶＥＬＬ／ＯＲＡＣＬＥ的Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ计算环境的系统平台设计与实现。     

用Delphi开发Client＼Server结构的数据库应用软件

Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ结构的数据库应用软件是网络数据库应用的重要分支,Ｄｅｌｐｈｉ在这方面有其独特的优势。本文以一个完整的例子讲述如何用Ｄｅｌｐｈｉ４（Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ版）开发两层的Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ数据库应用程序的具体方法。     

JDBC编程技巧

用Ｊａｖａ语言和数据库互联的接口ＪＤＢＣ开发独立于数据库平台的Ｃｌｉｅｎｔ／Ｓｅｒｖｅｒ数据库应用程序。     

Fifth generation and VLSI architectures

Most Western Governments (USA, Japan, EEC, etc.) have now launched national programmes to develop computer systems for use in the 1990s. These so-called Fifth Generation computers are viewed as “knowledge” processing systems which support the symbolic computation underlying Artificial Intelligence applications. The major driving force in Fifth Generation computer design is to efficiently support very high level programming languages (i.e. VHLL architecture).

Historycally, however, commercial VHLL architectures have been largely unsuccesful. The driving force in computer designs has principally been advances in hardware which at the present time means architectures to exploit very large scale integration (i.e. VLSI architecture).

This paper examines VHLL architectures and VLSI architectures and their probable influences on Fifth Generation computers. Interestingly the major problem for both architecture classes is parallelism; how to orchestrate a single parallel computation so that it can be distributed across an ensemble of processors.     

Organization of Parallel Query Processing in Multiprocessor Database Machines with Hierarchical Architecture

The development of database systems with hierarchical hardware architecture is currently a perspective trend in the field of parallel database machines. Hierarchical architectures have been suggested with the aim to combine advantages of shared-nothing architectures and architectures with shared memory and disks. A commonly accepted way of construction of hierarchical systems is to combine shared-memory (shared-everything) clusters in a unique system without shared resources. However, such architectures cannot ensure data accessibility under hardware failures on the processor cluster level, which limits their use in systems with high fault-tolerance requirements. In this paper, an alternative approach to construction of hierarchical systems is suggested. In accordance with this approach, the systems is constructed as an assembly of processor clusters with shared disks, with each cluster being a two-level multiprocessor structure with a standard strongly connected topology of interprocessor connections. A stream model for organization of parallel query processing in systems with the hierarchical architecture suggested is described. This model has been implemented in a prototype parallel database management system Omega designed for Russian multiprocessor computational systems MBC-100/1000. Our experiments show that the total performance of the processor clusters in the Omega system is comparable with that of the processor clusters with shared resources even in the case of great data skew. At the same time, the clusters of the Omega system are capable of ensuring a higher degree of data availability compared to the clusters with shared-memory architectures.     

On the single processor performance of simple lattice Boltzmann kernels

This report presents a comprehensive survey of the effect of different data layouts on the single processor performance characteristics for the lattice Boltzmann method both for commodity “off-the-shelf” (COTS) architectures and tailored HPC systems, such as vector computers. We cover modern 64-bit processors ranging from IA32 compatible (Intel Xeon/Nocona, AMD Opteron), superscalar RISC (IBM Power4), IA64 (Intel Itanium 2) to classical vector (NEC SX6+) and novel vector (Cray X1) architectures. Combining different data layouts with architecture dependent optimization strategies we demonstrate that the optimal implementation strongly depends on the architecture used. In particular, the correct choice of the data layout could supersede complex cache-blocking techniques in our kernels. Furthermore our results demonstrate that vector systems can outperform COTS architectures by one order of magnitude.     

多媒体会议系统分层通信结构及共算法研究

目前,多媒体会议系统的通信结构主要分为两种：集中式通信结构和全分布式通信结构。在远程多媒体会议系统中,这两种通信结构都很难满足多媒体会议系统的实时性要求。针对这两种通信结构的缺点与不足,该文提出了一种新的通信结构：分层通信结构。这种通信结构可有效减少远程多媒体会议系统的时间延迟。对于不同的媒体混合技术,我们分别给出了构造其最佳分层通信结构的方法及相应算法。实验数据表明,：相对于集中式通信结构和全分布式通信结构而言,分层通信结构可以有效减少远程多媒体会议系统的时间延尺,从而更好的满足远程多媒体会议系统的实时性要求。     

Architectures within the ESPRIT SPAN project

An overview is given of the SPAN project, which pooled the resources of numerous researchers in several countries to integrate symbolic and numeric computing on parallel systems. The resulting Kernel System architectures provided a central model for which two programming languages and two parallel-system architectures were developed. The Kernel System architecture, Parle high-level procedural language, Virtual Machine Code, Sprint processor architecture, and DICE distributed memory architecture are examined     

Energy efficient novel architectures for the lifting-based discrete wavelet transform

Energy efficient single-processor and fully pipelined architectures for the lifting-based JPEG2000's 5/3 two-dimensional (2D)-discrete wavelet transform are presented. The single processor performs both the row-and column-wise processing simultaneously, that is, full 2D transform with 100% hardware utilisation. In addition, the architecture uses minimum embedded memory. The fully pipelined architecture is obtained by replicating the single-processor block depending on the levels of decomposition with much lower memory requirement and higher throughput than the single processor involved in multi-level transforms. These architectures can be directly used in real-time image/video consumer applications to extend the battery life of portable systems.     

Reduction of cochannel interference in WCDMA cellular systems

In this paper, a novel cochannel interference reduction technique is proposed for wideband code division multiple access (WCDMA) cellular systems. Cochannel interference for the proposed cellular architecture is considered and analyzed. An analytic expression for the proposed method is derived. Simulation results demonstrate that the proposed method provides better signal-to-noise (S/N) ratio than the existing cochannel interference reduction methods. A significant reduction of cochannel interference is achieved compared to sectoring and omnidirectional architectures in the proposed microzoning architecture. In particular, it is shown here that the proposed architecture exhibits a larger number of users per cell while maintaining an adequate S/N ratio in comparison with other architectures.     

The 3DP: a processor architecture for three-dimensionalapplications

The 3DP (3-Dimensional Processor), a parallel-computing architecture that targets problems that have a 3-D numerical structure and require numerous calculations on 3-D vectors, is described. The 3DP architecture differs from traditional scalar architectures in that it operates directly on vectors. It differs from general parallel architectures in that it can solve problems that predict the behavior of highly coupled systems, and it differs from vector architectures in that it runs efficiently on length-3 vectors. Object-oriented programming on the 3DP and programming the 3DP in C++ are discussed. 3DP performance is reviewed, and the current implementation of the 3DP architecture, as an attached processor that plugs directly into Sun host VMEbus, is described     

基于协作式客户机/服务器系统的可复用构架

文章通过一个协作式客户机/服务器软件系统的实例阐明了设计不同系统体系可复用扩展软件构架的一种方法。笔者提出的构架,将使用构架描述语言进行定义,通过软件复用的三个层次(独立于应用域的,领域特有的和应用特有的),有机地组织起来。构架由可复用领域的特定黑盒构架模式和可扩展领域的特定白盒构架模式组成。文章重点阐述了软件构架中复用的不同层次以及构架如何实现扩展。     

A framework for analysis and design of software reference architectures

Context

A software reference architecture is a generic architecture for a class of systems that is used as a foundation for the design of concrete architectures from this class. The generic nature of reference architectures leads to a less defined architecture design and application contexts, which makes the architecture goal definition and architecture design non-trivial steps, rooted in uncertainty.

Objective

The paper presents a structured and comprehensive study on the congruence between context, goals, and design of software reference architectures. It proposes a tool for the design of congruent reference architectures and for the analysis of the level of congruence of existing reference architectures.

Method

We define a framework for congruent reference architectures. The framework is based on state of the art results from literature and practice. We validate our framework and its quality as analytical tool by applying it for the analysis of 24 reference architectures. The conclusions from our analysis are compared to the opinions of experts on these reference architectures documented in literature and dedicated communication.

Results

Our framework consists of a multi-dimensional classification space and of five types of reference architectures that are formed by combining specific values from the multi-dimensional classification space. Reference architectures that can be classified in one of these types have better chances to become a success. The validation of our framework confirms its quality as a tool for the analysis of the congruence of software reference architectures.

Conclusion

This paper facilitates software architects and scientists in the inception, design, and application of congruent software reference architectures. The application of the tool improves the chance for success of a reference architecture.