Microprogrammable peripheral controller

One of the most talked about microprocessor applications in the computer peripheral industry is device control. This paper presents a microsequencer-based general-purpose microprogrammable peripheral controller. This controller enables efficient and easy coupling between a wide range of I/O buses and peripherals. As an example, design details are given for interfacing a card reader onto an IBM standard I/O bus.     

Low cost computer graphics in engineering education

The Apple II is a personal computer which provides 6 color, raster graphics via a 280 h × 192 v frame buffer. A user-programmable MOS Technology 6502 CPU addresses 48 K bytes of RAM, 12 K of ROM. and 4 K of memory-mapped I/O. This system has been evaluated in a variety of applications for which one normally assumes higher resolution, higher cost graphics devices are needed.Examples were drawn from computer aided design, color microfilm previewing, cartography, and aircraft synthesis. The results were encouraging: low resolution raster scan graphics is surprisingly effective for a wide range of applications. As a result, a computer graphics laboratory, with a cluster of 10 Apples as its nucleus, was formed and has been functioning successfully for 4 terms.     

Design of a multimicroprocessor-controlled PABX: Continuing decreases in component costs mean that systems such as telephone branch exchanges can handle large data traffic relatively cheaply.

Problems encountered in the design of a multimicroprocessor-controlled private automatic branch exchange (PABX) using space division analogue switching concepts are discussed. The design organization includes pairs of groups of subscribers. Each group is controlled by a microprocessor with a private memory; the system also includes a common memory accessible by all the microprocessors. The maximum number of subscribers is 256 in each pair of groups; this is governed by the 8-bit word length of the microprocessors used. If the word length of the processor is doubled, the maximum number may reach 6000 subscribers per pair of groups; this is limited by the available addressing space because memory-mapped I/O control is used. A further increase in the number of subscribers per pair of groups may be achieved if memory space is not an obstacle, since the processor speed does not pose any limitation on the organization used for up to 110 000 subscribers per pair of groups. Expansion of such an organization scheme by adding more group pairs is possible; however, this makes hardware interfacing in the system slightly more complex.A complete design for a pair of groups controlled by two microprocessors and servicing 256 subscribers is described. The implementation of this design in the laboratory is discussed. The main requirements of multiprocessing were applied to the proposed PABX with regard to the logic, software and hardware design. The design of all the microprocessor circuits is given. All external circuits responsible for counting and storing dialled digits, generating telephone tones and interfacing are described in detail. The main programs and accompanying subroutines are discussed and their flowcharts are given. The complete design provided a satisfactory telephone service when realized in the laboratory. Finally, the advantages and disadvantages of the system are discussed.     

Product Profile

Floppy Disk Drive: FD360 micro-peripheral floppy disk drive operates under directions from Intel or National Semiconductor microprocessor system. Hardware interfaces and FDOS (Floppy Disk Operating Systems) available for Intellec-8, Intellec-8/Mod-80, IMP-16P, 16L, 8P. Features include format compatibility with IBM 3741, 3742, 3540 systems, built-in hardware track seek and seek verification, automatic head load/unload, operation with programmed I/O or DMA interfaces, sector buffering to enable asynchronous programmed I/O. Eight input, 16 output lines provide interfacing. Single drive configuration, $2350 (unit); 2 drives, $3000. Special interfaces available. – iCOM, Canoga Park, CA.     

差分编码实现通用I/O口串行异步通信的方法

针对微处理器片上串行异步通信接口灵活性欠佳的不足,给出了一种将微处理器通用I/O口扩展成串行异步通信口的方法。利用微处理器自身的定时器,结合有限状态机设计思想,采用差分编码原理在通用I/O口实现了串行异步通信,该方法可以灵活地设定通信帧格式与码元长度。通过示波器检测发送端口的波形,验证了此方法的可行性,在解决通信可靠性和稳定性的同时,为微处理器串行接口的扩展和非标准协议串行通信提供了一种方案,简化了传统串行通信端口的扩展方法。     

一种实现USB随机中断传输的设备驱动程序设计方法

USB具有方便快速等优点,已经发展成为一种比较普遍的计算机与外围设备之间的接口.但是,USB设备不能够用传统方式中断主计算机,而是提供中断端点,主机可以周期性地查询中断端点.由于USB设备发生中断的时间不确定性,这就使中断传输的设备驱动程序开发的难度加大.阐述了实现USB中断传输的设备驱动程序和应用程序的设计原则和方法,该方法具有很强的通用性,并经过实践证明具有很好的实用性.     

非标准VAX／VMS设备的I／O操作

本文介绍了不同驱动和谐实现ＶＡＸ／ＶＭＳ非标准设备Ｉ／Ｏ操作的方法，即通过映射系统的Ｉ／Ｏ空间、联结设备的中断向量，调用中断服务例程和／或中断后递交的ＡＳＴ例程，实现设备的Ｉ／Ｏ操作。文中给出了实现这种操作的具体步骤。     

Microprocessor Input/Output Architecture

There are at least as many different microprocessor input/output organizations, circuit configurations, and device types as there are microprocessor families and manufacturers. Due to the diversity of competing approaches and devices, their similarities and differences are not always evident. The fact that each manufacturer describes his approaches and devices differently, and the relative scarcity of formal text material on microprocessors, do not make the situation any better. In this short space there is no hope of comprehensively surveying all available approaches and devices (nor would I want to, even if space were available!). On the other hand, I can present an overview of basic microprocessor I/O organization and typical circuit configurations and devices. Using these concepts as a basis, one may be able to make comparisons between current and future approaches available commercially.     

Simulating asynchronous hardware on multiprocessor platforms: the case of AMULET1

Synchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Hence, recently, there has been a resurgence of interest in asynchronous digital design techniques which promise to liberate digital design from the inherent problems of synchronous systems. This activity has revealed a need for modelling and simulation techniques suitable for the asynchronous design style. The concurrent process algebra communicating sequential processes (CSP) and its executable counterpart, occam, are increasingly advocated as particularly suitable for this purpose. This paper focuses on issues related to the execution of CSP/occam models of asynchronous hardware on multiprocessor machines, including I/O, monitoring and debugging, partition, mapping and load balancing. These issues are addressed in the context of occarm, an occam simulation model of the AMULET1 asynchronous microprocessor; however, the solutions devised are more general and may be applied to other systems too. Copyright © 2001 John Wiley & Sons, Ltd.     

USB2．0传输类型分析

为了满足不同类型外围设备的设计与应用，USB传输协议定义了4种传输类型：控制传输、同步传输、中断传输和批量传输。例举了一个全速设备的端点描述符，从定义、结构、信息包大小、传输速度和错误检测等方面对4种传输类型进行了分析和研究。     

众核处理器中硬件支持的I/O虚拟化优化技术研究

众核处理器中I/O资源被多个处理器核所共享。I/O虚拟化实现了I/O资源的高效共享和安全隔离,被越来越多的处理器设计所采用。硬件支持的I/O虚拟化从体系结构设计时就考虑对I/O虚拟化的支持,提供了一个全面、高效的I/O虚拟化的解决方案。深入研究了硬件支持I/O虚拟化的两大关键技术——DMA重映射技术和中断重定向技术,提出了基于Hint的IOTSB Cache管理方法和基于失效队列的失效方法来对DMA重映射进行优化,提出了多层可操控的中断模型和灵活可控的中断重定向实现方法来对I/O中断重定向进行优化。测试结果表明,提出的硬件支持的I/O虚拟化优化方法以很低的I/O性能开销实现了I/O资源的高效共享,提供了几乎接近无虚拟化环境下的I/O性能。     

Advanced DMA controller for 16-bit microcomputer systems

The features of a DMA device designed for use with 286, 186, 086 and 088 Intel-type buses are given. The SAB 82258 is also an I/O controller. The principles of data transfer in various modes are detailed, with some examples of data transfer which may be controlled or modified to suit various environments. Methods of interfacing with a CPU are outlined. This includes programming and the use of the multiplexer channel.     

Communication between two microprocessors through common memory

Advances in integration have enabled the design of dual microprocessor systems on a single board for extra processing power. The problems of interfacing these processors are discussed and reasons for preferring shared memory communications rather than I/O are outlined. A system using two 6809 microprocessors is described with the technical problems that were encountered or anticipated in its design. Software developed uses the ‘producer consumer’ analogy and three solutions are demonstrated.     

一种32位异步嵌入式微处理器原型

异步集成电路设计技术很好地解决了深亚微米工艺条件下同步集成电路设计技术面临的问题。文中在对一系列关键技术进行研究的基础上,设计并实现了一款32位异步嵌入式微处理器原型。在基于宏单元异步集成电路设计流程的基础上,结合解同步技术,提出了异步嵌入式微处理器原型的设计流程。研究了如何实现异步嵌入式微处理器的精确异常、相关检测、同步异步接口和本地握手电路等。最后给出了原型的实现和初步的性能评测结果。     

实时嵌入式操作系统中核外I/O的实现

传统操作系统核内驱动的I/O结构无法满足嵌入式操作系统的需要，核外I/O技术的实现难点是如何将外部中断从核内引向核外，分析了基于信号机制的核外I/O的实现方法，并提出了一种由系统核心ISR直接跳转到核外驱动程序ISR的核外硬中断方法及其实现方法。     

内存映射文件及其在大数据量文件快速存取中的应用

分析了Win32系统下的虚拟内存系统模式及内存映射文件的工作机理,介绍了如何用Windows API将文件映射至内存,并通过实验数据得出,采用内存映射文件在对大数据量文件进行存取,其效率远远高于传统的基于I/O方式的数据存取。     

Performance characterization of multi-thread and multi-core processors based XML application oriented networking systems

There is a growing trend to insert application intelligence into network devices. Processors in this type of Application Oriented Networking (AON) devices are required to handle both packet-level network I/O intensive operations as well as XML message-level CPU intensive operations. In this paper, we investigate the performance effect of symmetric multi-processing (SMP) via (1) hardware multi-threading, (2) uni-processor to dual-processor architectures, and (3) single to dual and quad core processing, on both packet-level and XML message-level traffic. We use AON systems based on Intel Xeon processors with hyperthreading, Pentium M based dual-core processors, and Intel’s dual quad-core Xeon E5335 processors. We analyze and cross-examine the SMP effect from both highlevel performance as well as processor microarchitectural perspectives. The evaluation results will not only provide insight to microprocessor designers, but also help system architects of AON types of device to select the right processors.     

并行文件系统的设计

在大规模并行处理巨型机（ＭＰＰ）的设计中，提高Ｉ／Ｏ性能同提高计算能力和通信能力同样重要。并行文件系统（ＰＦＳ）在多个Ｉ／Ｏ结点的多个磁盘上，分布文件系统和文件的磁盘块，将文件读写在计算结点转化成多个对物理块的直接Ｉ／Ｏ请求，利用预读，预分配，磁盘缓冲式区和异步Ｉ／Ｏ增加Ｉ／Ｏ的并发生，在特定的文件使用模式下，也是ＭＰＰ应用的主要Ｉ／Ｏ模式，获得很高的Ｉ／Ｏ效率。     

NVMRA: utilizing NVM to improve the random write operations for NAND‐flash‐based mobile devices

NAND flash memory has become the major storage media in mobile devices, such as smartphones. However, the random write operations of NAND flash memory heavily affect the I/O performance, thus seriously degrading the application performance in mobile devices. The main reason for slow random write operations is the out‐of‐place update feature of NAND flash memory. Newly emerged non‐volatile memory, such as phase‐change memory, spin transfer torque, supports in‐place updates and presents much better I/O performance than that of flash memory. All these good features make non‐volatile memory (NVM) as a promising solution to improve the random write performance for NAND flash memory. In this paper, we propose a non‐volatile memory for random access (NVMRA) scheme to utilize NVM to improve the I/O performance in mobile devices. NVMRA exploits the I/O behaviors of applications to improve the random write performance for each application. Based on different I/O behaviors, such as random write‐dominant I/O behavior, NVMRA adopts different storing decisions. The scheme is evaluated on a real Android 4.2 platform. The experimental results show that the proposed scheme can effectively improve the I/O performance and reduce the I/O energy consumption for mobile devices. Copyright © 2015 John Wiley & Sons, Ltd.