日本已制成的若干台电子数字计算机的性能表

称}FACOM召22HITAC一103FACOM一41HITACwe3OITOSBAC一100体三极管120001500400020006000元件晶体二极管50000 2500变咸元件890015000250002000制长数数点豁字小重复频率换路十进制符号十12位定点,浮点200千周静态二进制符号 47位浮点,定点2邃千周动态十进制符号 7位定点,浮点200千周静态十进制符号 12位定点,浮点230千周动态十进制12位 符号定点,浮点210千周静态狱姗姗5.60定点浮点0 .350 .83 .3浮点减法 法 法0 .16定点0 .40.婆一1.30.邵0。30 .921 .81 .80 .806 .84 .06 .55 .71 .36 .8定点0 .304.邓6 .33加乘除度︵毫秒︶二…     

8087协处理器的应用

8087数值数据处理器(简称NDP)是一种专门为高效率地实现算术运算而设计的。它能对二进制整数,十进制数以及浮点实数进行操作,其数据长度为2～10字节范围内。指令系统不仅包含有各种不同的加、减、乘、除运算,而且还提供了     

求解不相关并行机调度问题的十进制多目标灰狼算法

针对不相关并行机调度问题,面向降低能源消耗和减少完工时间的目标,提出一种更高效的基于十进制整数编码的多目标灰狼算法.求解时,采用将资源配置与作业排序相结合的十进制整数编码方式,设计了针对多目标离散调度问题的两阶段位置更新机制.同时引入了N S GA-Ⅱ的精英保留策略,提高了算法的寻优能力,应用最大迭代次数停止准则结束循环并保留最优解.最后,通过数值实验与有代表性的前沿算法进行仿真对比,以验证所提算法的可行性与有效性.     

浮点与整数资源区别分配的SMT处理器取指策略

在同时多线程处理器中,各线程对于浮点和整数资源需求不同,合理分配线程的共享资源是提升处理器整体性能的重要因素。为此,提出一种浮点与整数资源区别分配的取指策略,合理分配各个线程对于浮点和整数资源的使用情况。实验结果表明,与ICOUNT,STALL等策略相比,该策略在算术平均IPC和调和平均IPC方面均取得一定的性能提升,同时其在处理浮点和整数混合型程序时也具有优势。     

大整数取模的快速运算

大整数取模运算是密码学应用的一种基本运算,尤其是在基于因子分解假设的公钥密码学中占有极其重要的地位。提出的m位和n位两个大整数快速取模算法,是利用分治法思想,将n位的大整数分解为n个独立十进制整数的组合,通过八次大整数乘法建立一个预处理表,能够有效地将大整数取模的计算复杂度降为[O(n(m-n))],经大量实验数据验证该算法的合理性和高效性。     

基于子元素排列组合的XML文档信息隐藏

分析XML文档的层次结构,提出基于XML子元素排列组合的信息隐藏算法。将待隐藏秘密信息转换成十进制整数,利用子元素的排列组合形成等价元素,根据等价元素与整数间的映射关系,采用等价元素置换方法将整数嵌入XML文档。实验结果和分析表明,该算法不改变XML文件大小,其隐蔽性和鲁棒性优于现有XML文档信息隐藏技术,且信息隐藏量较大,可以应用于XML网页保护和隐秘通信。     

MCS-96/196三字节浮点库

应用于MCS-96系列单片机的浮点库有许多.大多数是五字节(8位十进制数),运行速度慢.而在实际应用中,许多计算只需4位十进制数即可.     

求解多背包问题的混合蛙跳算法

针对多背包问题,提出一种改进的离散混合蛙跳算法。算法中对青蛙个体采用十进制整数编码方式,应用遗传算法中的交叉操作来对个体进行更新,扩展了传统混合蛙跳算法模型。将改进的算法用于多背包问题求解,仿真实验表明了所提算法的有效性。     

基于整数小波变换的图像压缩算法

IWT（integer wavelet transform）是一种基于提升格式整数小波变换的图像压缩算法.IWT比传统的浮点小波变换效率要高.在硬件实现时,整数运算比浮点运算便宜,基于提升格式的整数分解时所需的存储空间只是传统变换的一半.基于此考虑有损压缩,图像先作基于提升格式的整数分解,然后结合改进的EZW和自适应量程编码.在编码性能不受影响的情况下,此算法比Shaprio的EZW编码要快1.5倍.     

以十进制为中心的进制转换算法的设计与实现

从实际应用的角度出发,基于进制转换算法的基本原理,提出了以十进制为转换中心的进制转换算法,进行二、八、十和十六进制整数之间的转换。利用MFC,根据该算法,实现了二、八、十和十六之间的进制转换器,过程中提出了获取位权的算法。算法逻辑性强,实现简单方便。     

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition.     

基于混沌保密的USB软件加密狗及其反解密研究

提出了一种运用整数运算代替浮点运算的数字混沌保密改进算法,并将该方法用于USB软件加密狗的设计。该文分析了基于混沌技术的USB软件加密狗工作原理和工作过程,着重说明了PC主机与加密狗之间交换数据的详细过程。最后,通过对几种常见的破解方法的分析,表明了该加密狗较强的反解密性能。     

可在单片机上实现的语音混沌保密通信方法

针对目前数字混沌保密方法中计算量大的不足,提出了一种可在单片机上实现的改进混沌保密方法,并将该方法用于数字语音混沌保密通信。分析了该方法中运用整数运算代替浮点运算降低计算量的原理与过程,着重说明了改进的混沌算法在单片机上的实现。最后,在AT89C51单片机上成功进行了数字语音的混沌保密通信实验并取得了令人满意的结果。     

A new area-efficient BCD-digit multiplier

In the Internet of Things era, with millions of devices performing financial and commercial operations, decimal arithmetic has become very popular in the computation of many business and commercial applications, in order to maintain decimal rounding and precision. This paper proposes the design and implementation of a new algorithm for decimal multiplication oriented to area reduction. This algorithm is especially suitable for field programmable gate arrays (FPGA) and has thus been implemented on this kind of devices. Results show that the proposed BCD multiplication leads to a significant area reduction without decreasing system performance.     

Design and simulation of quantum-dot cellular automata serial decimal pipelined processor based on Turing machine model

The quantum-dot cellular automata (QCA) nanoscale computer technology is promising to overcome the limits of the microelectronic CMOS technology. Because the leading role of QCA wires, the serial data transfer/processing is preferable. The financial, Internet of Things, and control computer applications require direct processing of decimal information without representation and conversion errors. Because a QCA wire can be considered as a virtual tape with written binary symbols, a special version of Turing machine model can be used for a QCA computer implementation. Design of a novel QCA serial decimal pipelined processor based on the Turing machine model is presented. The processor uses the run-time tape reconfiguration for arithmetic processing of decimal operands encoded in the 5-bit Johnson-Mobius code. The proposed design demonstrates significant hardware simplification.     

C语言中浮点数的存储格式及其有效数字位数

总结了C语言中的单精度型（float）、双精度型（double）和长双精度（long double）浮点数的存储格式，并用简洁的C程序给出了验证；对其表示的十进制数的有效数字位数，从相对误差的角度，给出了判定方法及结论。     

A General Multi-step Algorithm for Voxel Traversing Along a Line

Traversing voxels along a three dimensional (3D) line is one of the most fundamental algorithms for voxel‐based applications. This paper presents a new 6‐connectivity integer algorithm for this task. The proposed algorithm accepts voxels having different sizes in x, y and z directions. To explain the idea of the proposed approach, a 2D algorithm is firstly considered and then extended in 3D. This algorithm is a multi‐step as up to three voxels may be added in one iteration. It accepts both integer and floating‐point input. The new algorithm was compared to other popular voxel traversing algorithms. Counting the number of arithmetic operations showed that the proposed algorithm requires the least amount of operations per traversed voxel. A comparison of spent CPU time using either integer or floating‐point arithmetic confirms that the proposed algorithm is the most efficient. This algorithm is simple, and in compact form which also makes it attractive for hardware implementation.     

Three wrongs make a right

When dealing with graphics operations that must be fast (like the inner loops of rendering algorithms), I usually like to do calculations with fixed-point arithmetic (that is, scaled integers) rather than floating point arithmetic. The exact scaling factor used can have some interesting effects on the speed and errors in the calculation. In this article, I'll give some titbits I've discovered or picked up from others about this. In particular, I'll talk about some of the advantages of using odd numbers of the form 2ⁿ-1 as scaling factors. The motivation for this discussion is the desire to do arithmetic on pixel values: red, green, blue, or alpha. These values are in the range 0...1, so all numbers you see here are positive. In the discussion that follows, I'll use floating point as a testbed and as scaffolding to derive integer formulas. All final calculations take place using only integer arithmetic     

Specification of hardware for interval arithmetic

Interval arithmetic, as it is standardized by the IEEE working group P1788 can be implemented by using floating point arithmetic units with directed rounding modes. The easiest way to represent an interval is by its two bounds. Simple formulas for the arithmetic operations can be applied. Our goal is to perform interval operations as fast as their floating point counterparts. Hence, we provide at least two units per operation. We also specify the operation for reverse multiplication (Neumaier in Vienna proposal for interval standardization, 2008) which can be implemented with the division unit. In this paper we do not care about optimization. Our primary intention is to give an easily understandable specification of hardware for interval arithmetic.     

Decimal shifting for an exact floating point representation

A floating point representation which permits exact conversion of decimal numbers is discussed. This requires the exponent to represent a power of ten, and thus decimal shifts of the binary mantissa are needed. A specialized design is analyzed for the problem of division by ten, which is needed for decimal shifting.