解同步电路中的功耗优化方法

针对解同步方法设计的异步电路存在冗余功耗的问题,提出一种功耗优化的解同步异步电路设计方法.首先以迭代结构乘法器为例分析操作数及电路操作行为对异步流水线功耗的影响;然后将窄数据特性及操作行为特性引入到解同步设计方法中,其中窄数据特性用于优化数据通路,操作行为特性用于优化控制通路;最后采用该方法对异步传输触发体系结构(TTA)微处理器计算内核进行功耗优化设计.实验结果表明,结构优化后的异步TTA微处理器内核功耗明显减少,约为解同步异步内核功耗的60%.     

一种解同步电路优化设计方法的研究和实现

解同步电路设计方法可以与现有EDA工具较好地兼容,可以极大地提高异步电路的设计效率.基于解同步电路的抽象模型--控制图,提出了一种解同步电路优化设计方法,优化过程由解同步电路的性能评价函数作为指导,在不影响电路性能的前提下有效地减小电路控制通路的面积.选取了一系列标准测试电路进行了实验,最终解同步电路控制通路所需的局部控制器数量减少了54%,C门的数量减少了76.3%.采用该设计方法,设计实现了0.35μm工艺条件下的32位解同步乘法器,实验结果表明,相对于传统的解同步电路设计方法,提出的优化设计方法可以在保持电路性能的前提下有效地减小电路的面积.     

AFMC:一种新的异步电路设计自动化流程

随着VLSI面临的功耗及时钟问题越来越突出,异步电路及其设计方法得到了广泛关注.基于宏单元的异步电路设计流程能够采用现有的同步EDA工具和设计流程将同步电路转变成相应的异步电路.在基于宏单元的异步电路设计流程的基础上提出了一种新的异步电路设计自动化流程,并与解同步异步电路设计自动化流程进行了比较.在UMC 0.18μm工艺下采用提出的自动化流程设计实现了一款DLX异步微处理器,实验结果表明该流程能够快速地进行异步电路设计,并且在异步电路的数据通路性能优化方面具有一定的优势.相对于解同步DLX微处理器,采用基于宏单元的异步设计自动化流程实现的异步DLX微处理器能够获得6%左右的性能提高.     

一种32位异步乘法器的研究与实现

提出基于宏单元（macrocell）的异步电路设计流程,由于在流程中尽量与现有的同步电路设计EDA工具兼容,降低了技术难度,提高了开发效率.基于该流程实现了0.35μm工艺条件下的32位异步乘法器.经过与相同工艺条件下,具有相同数据通路结构的同步乘法器比较,异步乘法器的性能与同步乘法器相当,而且面积更小、功耗更低.     

异步处理器设计中的关键技术研究

异步处理器解决了传统的同步处理器时钟偏移的问题,具有低功耗和高并行性等优点。本文着重分析了设计异步处理器的关键技术及实现方法,分析比较了当前异步处理器的实现方式,指出了异步处理器的研究方向和重点。并展望了异步处理器技术在媒体处理领域中的应用。异步处理器虽然还没有得到实际的广泛应用,但具有很高的研究价值。     

一种32位异步嵌入式微处理器原型

异步集成电路设计技术很好地解决了深亚微米工艺条件下同步集成电路设计技术面临的问题。文中在对一系列关键技术进行研究的基础上,设计并实现了一款32位异步嵌入式微处理器原型。在基于宏单元异步集成电路设计流程的基础上,结合解同步技术,提出了异步嵌入式微处理器原型的设计流程。研究了如何实现异步嵌入式微处理器的精确异常、相关检测、同步异步接口和本地握手电路等。最后给出了原型的实现和初步的性能评测结果。     

一种32位异步嵌入式微处理器原型

异步集成电路设计技术很好地解决了深亚微米工艺条件下同步集成电路设计技术面临的问题.文中在对一系列关键技术进行研究的基础上,设计并实现了一款32位异步嵌入式微处理器原型.在基于宏单元异步集成电路设计流程的基础上,结合解同步技术,提出了异步嵌入式微处理器原型的设计流程.研究了如何实现异步嵌入式微处理器的精确异常、相关检测、同步异步接口和本地握手电路等.最后给出了原型的实现和初步的性能评测结果.     

同步流密码机中E1接口的设计与实现

提出了同步流密码机中E1接口的一种设计与实现方法。介绍了低功耗单片机MSP430F149和E1接口芯片DS21348的特点,说明了设计过程并给出了E1接口的硬件连接图。为了使E1接口能够进行正确的数据交换和实现完全的数据同步,对DS21348内部控制寄存器进行了正确的设置。设计出的E1接口可以实现从物理线路上提取时钟信号及数据、去抖动处理、发送数据等功能。     

“腾越-Ⅱ”嵌入式异步微处理器的设计与实现

嵌入式系统对处理器功耗开销有严格的限制,异步电路技术可以作为设计低功耗处理器的有效方法之一。针对嵌入式多媒体应用,本文设计实现了一款低功耗异步微处理器——腾越-Ⅱ。处理器中包含一个异步TTA微处理器内核、一个同步TTA微处理器内核、两个存储控制器和多个外部通信接口。异步内核通过基于宏单元的异步电路设计方法实现,其它部分通过基于标准单元的半定制设计流程实现。处理器芯片采用UMC0.18μmCMOS工艺实现,基片面积为4.89×4.89mm2,工作电压为1.8V。经测试,处理器工作主频达到200MHz,且异步内核的功耗开销低于同步内核的50%。     

基于APB总线接口的USART IP核设计与验证

针对传统UART IP核设计中存在的使用场景单一、不能支持同步通信的不足，设计了一款基于APB总线接口的USART外设。采用模块化设计方式通过Verilog语言对APB总线数据传输模块、寄存器组模块、串行数据发送模块、串行数据接收模块、波特率发生模块进行了详细设计，并使用Simvision软件通过UVM验证方法学对电路的异步/同步通信功能进行验证。验证结果表明，设计的IP核在实现异步数据收发的基础上可实现基于SPI协议的同步数据收发，相较于传统的UART IP核设计，具有更强的普适性。     

An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design

Approximate computing is a popular field for low power consumption that is used in several applications like image processing, video processing, multimedia and data mining. This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier. The multiplier is the most essential element used for approximate computing where the power consumption is majorly based on its performance. There are several researchers are worked on the approximate multiplier for power reduction for a few decades, but the design of low power approximate multiplier is not so easy. This seems a bigger challenge for digital industries to design an approximate multiplier with low power and minimum error rate with higher accuracy. To overcome these issues, the digital circuits are applied to the Deep Learning (DL) approaches for higher accuracy. In recent times, DL is the method that is used for higher learning and prediction accuracy in several fields. Therefore, the Long Short-Term Memory (LSTM) is a popular time series DL method is used in this work for approximate computing. To provide an optimal solution, the LSTM is combined with a meta-heuristics Jellyfish search optimisation technique to design an input aware deep learning-based approximate multiplier (DLAM). In this work, the jelly optimised LSTM model is used to enhance the error metrics performance of the Approximate multiplier. The optimal hyperparameters of the LSTM model are identified by jelly search optimisation. This fine-tuning is used to obtain an optimal solution to perform an LSTM with higher accuracy. The proposed pre-trained LSTM model is used to generate approximate design libraries for the different truncation levels as a function of area, delay, power and error metrics. The experimental results on an 8-bit multiplier with an image processing application shows that the proposed approximate computing multiplier achieved a superior area and power reduction with very good results on error rates.     

基于FPGA数字乘法器的设计

数字乘法器是目前数字信号处理中运用最广泛的执行部件之一,本文设计了三种基于FPGA的数字乘法器,分别是移位相加乘法器、加法器树乘法器和移位相加—加法器树混合乘法器。通过对三种方案的仿真综合以及速度和面积的比较指出了混合乘法器是其中最佳的设计方案。     

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.     

基于FPGA数字乘法器的设计

数字乘法器是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA的数字乘法器．分别是移位相加乘法器、加法器树乘法器和移位相加-加法器树混合乘法器。通过对三种方案的仿真综合以及速度和面积的比较指出了混合乘法器是其中最佳的设计方案。     

Soundspace partitioning to increase communication efficiency in bird communities

Birds do not always vocalize at random, but may rather divide up soundspace in such a manner that they avoid overlap with the songs of other bird species. In effect, a high degree of communication efficiency can be achieved by many simultaneously active vocalists that finely integrate songs with minimal overlap. We describe this phenomenon from several recordings at our principal study location, near Volcano, California. The most-studied models for conceptualizing and studying such de-synchronized systems come from scheduling algorithms in computer science, where internet protocols involve packets of information that are broadcast widely; any collisions between them will corrupt the colliding packets so that they need to be resent. We have simulated some of these methods that might be appropriate for the soundspace of bird communities. Some features of these de-synchronized depend on specifics of the algorithms used.     

On high-performance parallel decimal fixed-point multiplier designs

High-performance, area and power efficient hardware implementation of decimal multiplication is preferred to slow software simulations in various key scientific and financial applications, where errors caused by converting decimal numbers into their approximate binary representations are unacceptable. This paper presents a parallel architecture for fixed-point 8421-BCD-based decimal multiplication. In essence, it applies a hybrid 8421–5421 recoding scheme to generate partial products, and accumulates them with 8421 carry-lookahead adders organized as a tree structure. In addition, we propose a 4221-BCD-based decimal multiplier that is built upon a novel 4221-BCD full adder; operands of this 4221 multiplier are directly represented in the 4221 BCD. The proposed 16 × 16 decimal multipliers are compared with other best-known decimal multiplier designs with a TSMC 90-nm technology, and the evaluation results show that the proposed 8421–5421 multiplier achieves the lowest delay and area, as well as the highest power efficiency, among all the existing hardware-based BCD multipliers.     

X-DSP浮点乘法器的设计与实现

为了满足高性能X-DSP浮点乘法器的性能、功耗、面积要求,研究分析了X型DSP总体结构和浮点乘法器指令特点,采用Booth 2编码算法和4∶2压缩树形结构,使用4级流水线结构设计实现了一款高性能低功耗浮点乘法器。使用逻辑综合工具Design Compiler,采用第三方公司0.13μm CMOS工艺库,对所设计的乘法器进行了综合,其结果为工作频率500MHz,面积67529.36μm2,功耗22.3424mW。     

一种低功耗常系数乘法器的设计

该文基于并行乘法器结构设计了一种新型的低功耗常系数乘法器。它采用了CSD(Canonical sign-digital)编码,W allace Tree乘法算法,结合采用了截断处理,变数校正的优化技术,实现了一种适用于DCT/IDCT变换的常系数乘法器。该乘法器的输入字长为15bits(Q3格式)输出字长为15bits(Q3格式),常系数字长为15bits(Q14格式)。采用SM IC0.18 um工艺进行综合,本设计的面积为13 974滋m 2,并在100M H z的时钟频率下功耗为0.69m w。通过与其它算法实现的乘法器进行分析与比较,说明了该设计在满足性能的同时,实现了较小的面积与较低的功耗。     

An AA-Sized Vibration-Based Microgenerator for Wireless Sensors

This paper deals with the vibration-to-electrical transducer that has an M-size form factor and generates a DC voltage that can power off-the-shelf integrated circuits. Vibration-powered wireless sensors obtain power from machine vibrations, human movement, or other forms of motion. The feasibility of incorporating micro power transducers (MPTs) with a voltage multiplier and rectifier to make a micro power generator (MPG) is demonstrated, that has the same size and shape as an AA battery. The AA-sized module includes a voltage multiplier and a large capacitor to produce the DC output