Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.     

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.     

低功耗低电源线噪声纳米CMOS全加器

提出一种低功耗低电源线噪声的纳米CMOS全加器。采用电源门控结构的全加器来降低纳米CMOS电路的漏电功耗,改进了传统互补CMOS全加器的求和电路,减少了所需晶体管的数目,并进一步对休眠晶体管的尺寸和全加器的晶体管尺寸进行了联合优化。用Hspice在45nmCMOS工艺下的电路仿真结果表明,改进后的全加器电路在平均功耗时延积、漏电功耗和电源线噪声等方面取得了很好的效果。     

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

Prodigious demand for fast performance-ultra low power electronic devices has insinuated the discovery of circuit style that promises reduced propagation delay (t _p ), as well as low power dissipation (PWR). MOS current mode logic (MCML) style has emerged as a promising logic style that offers high speed of operation at the expense of acceptable power dissipation. This paper proposes a MCML full adder which employs a load controller circuit. It compares MCML full adder with hybrid-CMOS full adder in terms of various design metrics in superthreshold as well as subthreshold regions. MCML topology with load controller offers a high speed of operation and low power dissipation in superthreshold region. Same circuit arrangement, when operated in subthreshold region also delivers higher operating speed with ultralow power dissipation compared to its hybrid-CMOS counterpart. Power dissipation analysis established MCML based full adder more robust compared to its hybrid-CMOS counterpart. In particular, MCML full adder design achieves 3.77× (2.38×) improvement in propagation delay, 10.43× (3.45×) improvement in average power dissipation, 39.43× (8.21×) lower power-delay product (PDP) and 149.07× (19.55×) improvement in energy-delay product (EDP) in superthreshold (subthreshold) regions of operation at 16-nm technology node. The above results are also validated using TSMC’s industry standard 0.18-μm technology model parameters and a similar trend is observed in the design metrics of the MCML and hybrid-CMOS full adder circuits. In addition, noise performance of the above mentioned circuits is also carried out. It is observed that the noise induced by the hybrid-CMOS full adder is about 14× to that of the MCML full adder.

     

子字并行加法器的研究与实现

子字并行加法器能够有效提高多媒体应用程序的处理性能。基于门延迟模型对加法器原理及性能进行了分析,设计了进位截断和进位消除两种子字并行控制机制。在这两种机制的指导下,实现了多种子字并行加法器,并对它们的性能进行了比较和分析。结果表明进位消除机制相对于进位截断机制需要较短的延时,较少的逻辑门数以及较低的功耗。在各种子字并行加法器中,Kogge-Stone加法器具有最少的延迟时间,RCA加法器具有最少的逻辑门数和最低的功耗。研究结果可以用于指导子字并行加法器的设计与选择。     

Certain investigations in achieving low power dissipation for SRAM cell

The modern semiconductor industry is evolving quite rapidly. Portable and mobile devices are becoming smaller every day and there is also a growing demand for longer battery power. With these demands it is important for researchers to focus on the leakage power in stand-by mode. The SRAM was designed to accurately communicate with CPU, DSP, processor and low-power applications, such as battery-life handheld devices. For some days now, the design engineer focuses mainly on the production of large-capacity memories, high bandwidth and low energy consuming memories. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This Paper Describes the SRAM architecture designed for the reduction of power consumption or power leakages using sleep transistor and MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) techniques. This helps in the reduction of the CMOS transistor leakages. This paper incorporates multiple threshold strategies to give the proposed high speed, increased reliability and low leakage current of the updated 8T SRAM cell in stand-by memory cell mode. Based on the parameters like power dissipation at a different temperature, read voltage, write voltage, read delay, write delay, compared to the previously designed SRAM architecture of 6T, 7T, 8T and 13T we get low power consumption in our designed 8T SRAM architecture. The simulations are conducted with the UMC 55 nm technology Cadence Virtuoso method.     

基于互补电阻开关的忆阻乘法器设计

现有的忆阻算术逻辑多采用单个忆阻器作为存储单元,在忆阻交叉阵列中易受到漏电流以及设计逻辑电路时逻辑综合复杂度高的影响,导致当前乘法器设计中串行化加法操作的延时和面积开销增加。互补电阻开关具有可重构逻辑电路的运算速度和抑制忆阻交叉阵列中漏电流的性能,是实现忆阻算术逻辑的关键器件。提出一种弱进位依赖的忆阻乘法器。为提升忆阻器的逻辑性能,基于互补电阻开关电路结构,设计两种加法器的优化方案,简化操作步骤。在此基础上,通过改进传统的乘法实现方式,并对进位数据进行拆解,降低运算过程中进位数据之间的依赖性,实现并行化的加法运算。将设计的乘法器映射到混合CMOS/crossbar结构中,乘法计算性能得到大幅提高。在Spice仿真环境下验证所提乘法器的可行性。仿真实验结果表明,与现有的乘法器相比,所提乘法器的延时开销从O(n²)降低为线性级别,同时面积开销降低约70%。     

Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node

This paper presents a FinFET-based static 1-bit full adder cell that helps to recover the huge penalty in performance, while staying quite close to the minimum energy point. The proposed design offers higher computing speed (by 7.96×) and lower energy (by 5.86×), lower energy-delay product (EDP) (by 21.08×) at the expense of higher power dissipation (by 1.36×) compared to its MOSFET counterpart. It proves its robustness against process variations by featuring tighter spread in power distribution (by 3.20×), in delay distribution (by 4.70×), in PDP (power-delay product) distribution (by 3.35×) and in EDP distribution (by 3.14×) compared to its MOSFET counterpart. The proposed design achieves these improvements due to employment of new FinFET technology in the full adder design. Multi-gate devices in this technology are less affected by random dopant fluctuation (RDF) and short-channel effects such as threshold voltage rolloff, drain-induced barrier lowering (DIBL), etc. To establish that our design is better this paper analyzes five more 1-bit full adder cells and compares them with the proposed design in terms of power, delay and PDP. We perform simulation using 32-nm Predictive Technology Model (PTM) parameters on SPICE.

     

高性能桶形整数加法器的设计

为了提高加法器的运算速度,提出了一种新型并行整数加法算法——桶形整数加法算法。该加法器以半加器为基础,将并行与迭代反馈思想相结合,根据每轮迭代后进位链的值判断是否已经累加结束,可以在保持低功耗的同时提高运算速度。仿真结果表明,该桶形整数加法器在面积少量增加的基础上,速度提高明显。     

Low power adiabatic logic based on FinFETs

With the aggressive scaling of device technology,the leakage power has become the main part of power consumption,which seriously reduces the energy recovery efciency of adiabatic logic.In this paper,a novel low-power adiabatic logic based on FinFET devices has been proposed.Due to the lower leakage current,higher on-state current and design flexibility of FinFETs,the proposed adiabatic logic shows considerable power reduction,performance improvement and area saving compared with CMOS adiabatic logic.An 8-state clock chain as the test circuit has been demonstrated based on the 32-nm FinFET Predictive Technology Model.The simulation results show that adiabatic circuit based on FinFET devices achieves a power reduction of up to84.8%and a limiting frequency of up to 55 GHz.     

Iterative signal reconstruction of deliberately clipped SMT signals

Staggered MultiTone(SMT)is a modulation technique showing significantly reduced Adjacent Channel Leakage Ratio(ACLR)resulting in a more compact Power Spectrum Density(PSD)for the transmitted signal,than the well-known and already widely adopted Orthogonal Frequency Division Multiple Access(OFDMA)scheme.However,the unique spectral properties of an SMT signal could be degraded by a non-linear element(e.g.a Power Amplifier(PA))in the transmitter.Deliberate baseband clipping can be applied to the transmitted signal,reducing the notable high Peak-to-Average Power Ratio(PAPR).The objective of this paper is to give a brief introduction to the SMT scheme,with a special emphasis on deliberate clipping efects and their compensation.The paper introduces two receiver-oriented iterative methods aiming at the restoration of the baseband Bit Error Rate(BER)performance of a non-clipped signal.The methods are evaluated and compared based on numerical simulations.The paper concludes with the selection of a possible candidate for use in systems applying deliberately clipped SMT signals.     

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.     

To implement positive feedback adiabatic logic (PFAL)—NAND technique on low power Zigbee applications for processor applications

In recent years, field of Microprocessor and system world, where Zigbee is one of most important device for collect and transmitting the information from patient body and particular place to remote stations with efficient way. Power consumption is most important one for wireless devices. In present, most of the wireless devices are designed and developed by various design methodologies. Where logical system is complex for designing the wireless devices. In this paper, we propose a novel method of positive feedback adiabatic logic (PFAL) NAND technique for low power Zigbee applications for processor field. Here to implement positive feedback adiabatic logic – NAND technique on low power Zigbee applications is to be proposed. It employs the concept of adiabatic charge recovery. The circuit design has the less power consumption for the application of Zigbee low power mode this become critical concern. The adiabatic logic refers to a system in which a transition may occur without energy that is in the form of heat. It is the low power circuits which help to use reversible logic to conserve energy. The adiabatic circuits are operating on the principle of adiabatic charging and discharging process. It is to be used for partial energy recovery circuit and it has the lowest energy consumption which is compared to similar relatives. It is the best robustness which is against technological parameter variations.     

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

Design and analysis of high-speed 8-bit ALU using 18 nm FinFET technology

All modern computational devices consist of ALU. With increase in complexity of software and the consistent shift of software towards parallelism, high speed processors with hardware support for time consuming operations such as multiplication would benefit. Smaller, compact devices such as IoT devices need to run software such as security software and be able to offload computation cost from the cloud. In this paper, a high speed 8-bit ALU using 18 nm FinFET technology is proposed. The arithmetic and logical unit consists of fast compute units such as Kogge Stone fast adder and Dadda multiplier along with basic logic gates. In this paper, an ALU with each compute unit optimized for speed is proposed, while responsibly consuming area. Dadda multiplier is of 8 × 8 architecture as opposed to conventional approach of 4 × 4 making it a true 8-bit ALU. Simulation and analysis is done using Cadence Virtuoso in Analog Design Environment. The transistor count of proposed design is 5298, the power consumption is 219 µW and maximum delay is 166.8 ps. The design is also expected to consume a maximum of one clock cycle for any computation.

     

Implementing a one-bit reversible full adder using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technique is one of the emerging and promising nanotechnologies. It has considerable advantages versus CMOS technology in various aspects such as extremely low power dissipation, high operating frequency and small size. In this paper, designing of a one-bit full adder is investigated using a QCA implementation of Toffoli and Fredkin gates. Then, a full adder design with reversible QCA1 gates is proposed regarding to overhead and power savings. Our proposed full adder design is more preferable when considering both circuit area and speed. The proposed design uses only two QCA1 gates and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells.     

低成本的STC单片机的导航授时系统设计

针对国内导航系统与授时系统的发展现状,将两个系统合理地结合在一起并以STC12C5A单片机作为整个系统控制单元,设计出的导航授时服务系统成本低、功耗低。给出了系统的硬件设计和软件流程,同时介绍了上位机软件的模块化设计思想。经过测试,该系统可以在户外或室内对运动的载体实行导航定位,当系统结合计算机运行时能对计算机进行授时...     

Novel designs of nanometric parity preserving reversible compressor

Reversible logic is a new field of study that has applications in optical information processing, low power CMOS design, DNA computing, bioinformatics, and nanotechnology. Low power consumption is a basic issue in VLSI circuits today. To prevent the distribution of errors in the quantum circuit, the reversible logic gates must be converted into fault-tolerant quantum operations. Parity preserving is used to realize fault tolerant in this circuits. This paper proposes a new parity preserving reversible gate. We named it NPPG gate. The most significant aspect of the NPPG gate is that it can be used to produce parity preserving reversible full adder circuit. The proposed parity preserving reversible full adder using NPPG gate is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. Compressors are of importance in VLSI and digital signal processing applications. Effective VLSI compressors reduce the impact of carry propagation of arithmetic operations. They are built from the full adder blocks. We also proposed three new approaches of parity preservation reversible 4:2 compressor circuits. The third design is better than the previous two in terms of evaluation parameters. The important contributions have been made in the literature toward the design of reversible 4:2 compressor circuits; however, there are not efforts toward the design of parity preservation reversible 4:2 compressor circuits. All the scales are in the nanometric criteria.     

纳米级CMOS电路的漏电流及其降低技术

随着CMOS工艺的进一步发展，漏电流在深亚微米CMOS电路的功耗中变得越来越重要。因此，分析和建模漏电流的各种不同组成部分对降低漏电流功耗非常重要，特别是在低功耗应用中。本文分析了纳米级CMOS电路的各种漏电流组成机制并提出了相应的降低技术。     

Deadline-aware multi-objective IoT services placement optimization in fog environment using parallel FFD-genetic algorithm

Nowadays, Internet of things has become as an inevitable aspect of humans’ IT-based life. A huge number of geo-distributed IoT enabled devices such as smart phones, smart cameras, health care systems, vehicles, etc. are connected to the Internet and manage users’ applications. The IoT applications are generally time sensitive, so that giving them up to Cloud and receiving the response may violate their required deadline, due to distance between user device and centralized Cloud data center and consequently increasing network latency. Fog environment, as an intermediate layer between Cloud and IoT devices, brings a smaller scales of Cloud capabilities closer to user location. Processing real time applications in Fog layer helps more deadlines to be met. Although Fog computing enhances quality of service parameters, limited resources and power of Fog nodes is a challenge in processing applications. Furthermore, the network latency is still an issue for communications between applications’ services and between user device and Fog node, which seriously threatens deadline condition. Regarding to mentioned points, this paper proposes a 3-partite deadline-aware applications’ services placement optimization model in Fog environment which optimizes total power consumption, total resources wastage, and total network latency, simultaneously. The proposed model prioritizes applications in 3 levels based on their associated deadline, and then the model is solved using a parallel model of first fit decreasing and genetic algorithm combination. Simulations results indicates the superiority of proposed approach against counterpart algorithms in terms of reducing power consumption, resource wastage, network latency, and service rejection rate.