Dual-mode floating-point adder architectures

Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.     

子字并行加法器的研究与实现

子字并行加法器能够有效提高多媒体应用程序的处理性能。基于门延迟模型对加法器原理及性能进行了分析,设计了进位截断和进位消除两种子字并行控制机制。在这两种机制的指导下,实现了多种子字并行加法器,并对它们的性能进行了比较和分析。结果表明进位消除机制相对于进位截断机制需要较短的延时,较少的逻辑门数以及较低的功耗。在各种子字并行加法器中,Kogge-Stone加法器具有最少的延迟时间,RCA加法器具有最少的逻辑门数和最低的功耗。研究结果可以用于指导子字并行加法器的设计与选择。     

Effective RCA design using quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is a transistor less technology alternative to CMOS for developing low-power, high speed digital circuits. Adder circuits are broadly employed in all digital computation systems. In this paper, a novel coplanar QCA full adder circuit is proposed which is designed with minimum number of QCA cells. The proposed full adder requires only 13 QCA cells, an area of 0.008 μm² and delay of about 2 clock cycles to implement its function. Then an efficient 4-bit Ripple Carry Adder (RCA) is designed based on the proposed full adder that performs higher end addition in an effective way. Simulations results are obtained precisely using QCA designer tool version 2.0.3. Also the simulation results shows that the proposed 4-bit Ripple Carry Adder (RCA) requires only 70 QCA cells, an area of 0.18 μm² and delay of about 5 clock cycles to implement its function with enhanced performance in terms of latency, area and QCA Cost. From the comparisons, it is found that our work achieves over 55% improvement in QCA cell count.     

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.     

数字信号处理器中高性能可重构加法器设计

设计一款适用于高性能数字信号处理器的16位加法器。该加法器结合条件进位选择和条件“和”选择加法器的特点,支持可重构,可以进行2个16位数据或者4个8位数据的加法运算,同时对其进位链进行优化。相对于传统的条件进位选择加法器,在典型工作条件下,采用0.18μm工艺库标准单元,其延时降低46%,功耗降低5%。     

GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology

The Carry Select Adder (CSLA) is one of the fastest multi-bit adder architectures being used in various high speed processors. The CSLA is fast but compromises on the area and power consumption due to its complex architecture when implemented using standard CMOS logic. In this work, an alternate implementation of the CSLA architecture is done using Gate Diffusion Input (GDI) logic; instead of the CMOS logic. This approach simplifies the overall architectural dimensions due to reduction in transistor count as well as the power consumption. In this work, various types of CSLA architectures are implemented using the GDI logic and compared with their CMOS logic counterparts in terms of average power, delay and transistor count in 45 nm technology node. The comparative analysis clearly shows that GDI based circuits are better compared to CMOS logic implementations.     

一种改进的反码加法器设计

传统的加法器在有符号数相加时需将操作数转化为补码形式进行运算,运算结束将计算结果再转化为原码。为减少关键路径延迟,在标志前缀加法器的基础上,提出一种改进的反码加法器,将常用反码加法器中的加一单元合并到加法运算中。在SMIC 0.18 μm工艺下,将改进的64位反码加法器与常用的64位补码加法器进行比较,数据显示面积减少了39.1%,功耗降低了39.9%,关键路径延迟降低了5.1%。结果表明,改进的反码加法器性能较优。     

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.     

Comparative study of FFA architectures using different multiplier and adder topologies

Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.

     

Lane of parallel through carry in ternary optical adder

At the present 50 to 100 microseconds are necessary for a liquid crystal to change its state from opacity to clarity; 1.14×10-5 microseconds are however proved to be enough for light to pass through a clarity liquid crystal device. Rooted from this great difference in time, an optical adder was constructed with parallel through carry lanes (PTCL) composed of liquid crystals. Because all carries in PTCL process in parallel, the carry delay in the ternary optical computer's adder is avoided. Eliminating the carry delay in adder of ternary optical computer by physical means, the PTCL is also applicable for other types of optical adders. Moreover a light diagram of the adder and one PTCL structure are provided.     

FPGA implementation of XOR-MUX full adder based DWT for signal processing applications

In the recent past there is a rapid development in the field of digital technology especially in signal processing and image processing based applications Excellent performance high speed, compactable in size low power and less delay are the essential needs of the devices used for applications such as signal processing, audio processing and software define radio and so on. Particularly, digital gadgets are prone to have more critical logic size and power consumption and take large area in VLSI Implementation due to arithmetic operations of adders and multiplier designs. Thus priority architecture of Digital Wavelet Transform (DWT) is affected as it comprises a number of Filter banks in level basics, thus all Filter banks have number of adders and multipliers due to coefficient decompositions of low and high pass filters. On this n-size repeated filter logic takes more logic size and power consumption. Here, the proposed work presents a novel approach of DWT by replacing conventional adders and multipliers with XOR-MUX adders and Truncations multipliers thereby reducing the 2n logic size to n-size logic. Finally, the proposed DWT architecture designed in VHDL and also implemented in FPGA XC6SLX9-2TQG144 proved the performance in terms of delay, area and power.     

Performance enhancement of efficient process based on Carry-Skip Adder for IoT applications

IoT provides a platform for every device to be connected by means of a stable internet connection. The interoperability of the devices helps to communicate and exchange data between one another and increases the power consumption of devices. When creating a new IoT system or rebuilding the existing ones, the low power circuit design is considered as an essential factor. In the low power circuit design, the most challenging aspect to overcome is to reduce the leakage power, because the battery-operated devices are fast in draining energy when left long in the standby mode. Reducing the delay of a ripple carry adder can be only accomplished with Carry-Skip Adder (CSA) with minimal effort when compared to other techniques like a carry-look ahead adder. The carry skip adder belongs to the family of bypass adders, and its main aim is to improve the worst-case delay of the IoT device based on its area and power consumption. The CSA used in the proposed method for the IoT processor helps to increase the performance of the system relative to average power dissipation, leakage power, power delay product, and propagation delay.     

VLSI中加法器的一种高效自测试设计

基于算术加法测试生成,提出了VLSI中加法器的一种自测试方案:加法器产生自身所需的所有测试矢量.通过优化测试矢量的初值改进这些测试矢量,提高了其故障侦查、定位能力.借助于测试矢量左移、逻辑与操作等方式对加法器自测试进行了设计.对8位、16位、32位行波、超前进位加法器的实验结果表明,该自测试能实现单、双固定型故障的完全测试,其单、双故障定位率分别达到了95.570%,72.656%以上.该自测试方案可实施真速测试且不会降低电路的原有性能,其测试时间与加法器长度无关.     

高效缩1码模2n+1加法器设计与优化

针对目前存在的缩1码模2~n+1加法器的优缺点,设计出一个有效的基于进位选择的缩1码模2~n+1加法器。在模加法器的进位计算中,采用进位选择计算代替传统的进位计算,进位计算前缀运算量明显减少。分析和实验结果表明,对于比较大的n值,进位选择缩1码模2~n+1加法器在保持较高运算速度的前提下,有效地提高了集成度。     

一种基2冗余符号数加法的改进算法

冗余符号数加法器满足了对加法器高速度和高精度的要求。该文针对二进制符号数加法传统算法的不足，提出了一种改进算法，设计了相应的加法电路。它采用3级结构实现加法器，结构简单而规则，中间进位与中间和都仅需要1bit编码。与传统结构相比，该算法实现的电路速度更快、面积更小、动态功耗更少。     

Area and delay efficient GDI based accuracy configurable adder design

Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, whereas the lower bound of their critical path delay of n bit adder is Ὠ(log n). To achieve a minimum critical path delay lower than Ὠ(log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI (Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain. This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64-bit adder provides up to 23%, 34% and 95% reductions in area, power and delay, respectively compared to those of the existing adder.     

Formal proof of integer adders using all-prefix-sums operation

Addition of two binary numbers is a fundamental operation in electronic circuits.Several integer adder architectures have been proposed.Their formal properties are well known,but the proofs are either incomplete or difficult to find.In this paper,we present a formal proof for the correctness of prefix adders.Both sequential and parallel algorithms are formalized and proved.In contrast to previous proofs using higher order functions and rewriting systems,our work is based on first order recursive equations,which are familiar to the computer arithmetic community and are therefore understandable by people working on VLSI circuit design.This study sets up a basis for further work on formal proofs of computer arithmetic algorithms.     

Area and power efficient pipelined hybrid merged adders for customized deep learning framework for FPGA implementation

With the rapid growth of deep learning and neural network algorithms, various fields such as communication, Industrial automation, computer vision system and medical applications have seen the drastic improvements in recent years. However, deep learning and neural network models are increasing day by day, while model parameters are used for representing the models. Although the existing models use efficient GPU for accommodating these models, their implementation in the dedicated embedded devices needs more optimization which remains a real challenge for researchers. Thus paper, carries an investigation of deep learning frameworks, more particularly as review of adders implemented in the deep learning framework. A new pipelined hybrid merged adders (PHMAC) optimized for FPGA architecture which has more efficient in terms of area and power is presented. The proposed adders represent the integration of the principle of carry select and carry look ahead principle of adders in which LUT is re-used for the different inputs which consume less power and provide effective area utilization. The proposed adders were investigated on different FPGA architectures in which the power and area were analyzed. Comparison of the proposed adders with the other adders such as carry select adders (CSA), carry look ahead adder (CLA), Carry skip adders and Koggle Stone adders has been made and results have proved to be highly vital into a 50% reduction in the area, power and 45% when compared with above mentioned traditional adders.     

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition.