硅牌键合技术的研究进展

硅片键合技术是指通过化学和物理作用将硅片与硅片、硅片与玻璃或其它材料紧密地结合起来的方法.硅片键合往往与表面硅加工和体硅加工相结合,用在MEMS的加工工艺中.常见的硅片键合技术包括金硅共熔键合、硅/玻璃静电键合、硅/硅直接键合以及玻璃焊料烧结等.文中将讨论这些键合技术的原理、工艺及优缺点.     

碳化硅直接键合机理及其力学性能研究

随着碳化硅(SiC)材料的MEMS器件在恶劣环境测量中的应用前景和迫切需求,进行了碳化硅的直接键合实验.研究了工艺条件对键合样品力学性能的影响,同时借助激光共聚焦扫描显微镜(CLSM)、扫描电子显微镜(SEM)、能谱仪(EDS)和拉曼光谱仪等对碳化硅键合样品界面的微观结构进行了分析.结果表明:退火温度和加载压力是影响键合效果的关键性因素.当退火温度为1 300℃,加载压力为3 MPa和退火时间为3 h时,此时键合样品的气密性非常好,力学性能达到最佳,键合强度2 MPa.最后通过样品微观界面分析表明碳化硅直接键合的机理为界面氧化硅过渡层的形成及粘性流动与碳化硅和碳化硅的熔融直接键合.     

硅片键合技术的研究进展

硅片键合技术是指通过化学和物理作用将硅片与硅片，硅片与玻璃或其它材料紧密地结合起来的方法，硅片键合往往与表面硅加工和体硅加工相结合，用在MEMS的加工工艺中，常见的硅片键合技术包括金硅共熔键合，硅／玻璃静电键合，硅／硅直接键合以及玻璃焊料烧结等，文中将讨论这些键合技术的原理，工艺及优缺点。     

采用线阴极的快速阳极键合方法

在平板阴极和点阴极方式做阳极键合时,时间-电流特性、键合速度、结合界面质量等都有所不同。通过建立力学和电学模型,分析了不同阴极形状对阳极键合的时间、强度以及结合界面特性的影响。根据模型分析,采取了线阴极工作方式做阳极键合,样品的键合区扩散时间只需要84s。结合界面无空洞,键合强度为16.7MPa。     

硅片低温键合湿化学法表面活化工艺研究

探讨了使用湿化学法对硅片表面进行活化,完成硅圆片低温直接键合的流程.通过对不同活化流程细节的分析,以及实际的实验结果,对不同的工艺流程的键合效果进行比较.提出采用浓HNO3进行表面活化的方法相对于采用H2SO4以及HF效果要好.其在Si片表面生成的多孔结构氧化层有利于键合.此外,混合了微量HF的活化液由于HF活性较大,配量不易控制,在实际实验室环境中并不实用.文中还给出了实际键合样片的红外图像以及拉伸曲线.     

表面有微结构的硅片键合技术

针对表面带有微结构硅晶圆的封装展开研究,以采用Ti/Au作为金属过渡层的硅—硅共晶键合为对象,提出一种表面带有微结构的硅—硅共晶键合工艺,以亲水湿法表面活化处理降低硅片表面杂质含量,以微装配平台与键合机控制键合环境及温度来保证键合精度与键合强度,使用恒温炉进行低温退火,解决键合对硅晶圆表面平整度和洁净度要求极高,环境要求苛刻的问题。高低温循环测试试验与既定拉力破坏性试验结果表明:提出的工艺在保证了封装组件封装强度的同时,具有工艺温度低、容易实现图形化、应力匹配度高等优点。     

数据输入界面设计

一个数据库应用程序需要管理大量相关的数据,数据的输入是必不可少的。因数据表中存在大量的主外键联系（如教师表中的学院字段）,因此当一个表中存在外键时,外键的输入不能与表中其他字段一样直接输入其ID号,可以使用以前介绍的主细表联接方法,将主外键联接起来,通过选择的方法输入,可避免用户的输入错误。这里仅就本系统中几个关键的数据输入界面进行重点相关讲解,其他的界面大致相似,可以参照实现。     

应力型微悬臂梁生化传感器响应机理研究进展

针对静态微悬臂梁表面特异性结合产生表面应力信号的响应机制问题,介绍了微悬臂梁生化传感器的工作原理,阐述了应力响应机制的简化模型,从纵向界面上和横向分子间2个方面对特异性吸附引起的悬臂梁表面应力的变化进行了剖析,讨论了界面能变化、位阻作用、静电力、氢键作用等与表面应力大小及方向之间的关系,总结了应力型微悬臂梁生化传感器的响应机理的研究。     

可合可分 索尼SRS-M55

738元800-820-1288www.sony.com.cnSRS-M55音箱分为左右两个部分,可分可合——分时,水平垂直放置皆可;合时,自动回缩装置能够实现一键伸缩。合拢后,音箱大致与一个500ml矿泉水瓶相     

Si基Cu/NiFe薄膜的生长及其粘附特性研究

微机械(MEMS)工艺和集成电路(IC)工艺中,在硅(Si)片上电铸高深宽比坡莫(NiFe)合金材料常出现脱落现象.提出了一种电铸NiFe合金材料的新方法,这种方法制作的合金薄膜厚度达200 μm时不脱落.此方法即对等离子刻蚀后的硅片溅射种子层铜(Cu),然后对种子层进行电镀,当其厚度达到约15 μm时,再进行NiFe合金的电铸.本文用扫描电镜、x射线衍射仪和剥离实验研究了薄膜粘附特性.研究结果表明当对种子层电镀后,随着Cu种子层厚度的增加,Cu/NiFe薄膜与基体的粘附强度增加,而薄膜的残余应力降低;同时Cu膜表面粗糙度增加,也增加了NiFe膜与Cu膜的粘附强度.     

Low temperature wafer direct bonding

A pronounced increase of interface energy of room temperature bonded hydrophilic Si/Si, Si/SiO₂, and SiO₂/SiO ₂ wafers after storage in air at room temperature, 150°C for 10-400 h has been observed. The increased number of OH groups due to a reaction between water and the strained oxide and/or silicon at the interface at temperatures below 110°C and the formation of stronger siloxane bonds above 110°C appear to be the main mechanisms responsible for the increase in the interface energy. After prolonged storage, interface bubbles are detectable by an infrared camera at the Si/Si bonding seam. Desorbed hydrocarbons as well as hydrogen generated by a reaction of water with silicon appear to be the major contents in the bubbles. Design guidelines for low temperature wafer direct bonding technology are proposed     

Fabrication of silicon and oxide membranes over cavities usingion-cut layer transfer

Silicon and oxide membranes were fabricated using an ion-cut layer transfer process, which is suitable for sub-micron-thick membrane fabrication with good thickness uniformity and surface micro-roughness. After hydrogen ions were implanted into a silicon wafer, the implanted wafer was bonded to another wafer that has patterned cavities of various shapes and sizes. The bonded pair was then heated until hydrogen-induced silicon layer cleavage occurred along the implanted hydrogen peak concentration, resulting in the transfer of the silicon layer from one wafer to the other. Using this technique, we have been able to form sealed cavities and channels of various shapes and sizes up to 50-μm wide, with a 1.6-μm-thick silicon membrane. As a process variation, we have also fabricated silicon dioxide membranes for optically transparent applications     

Low-temperature wafer bonding: a study of void formation and influence on bonding strength

The void formation has been systematically observed for low-temperature (120/spl deg/C and 400/spl deg/C) Si-Si and SiO/sub 2/-SiO/sub 2/ wafer bonding techniques in function of the annealing time (from 70 to 595 h), pressure (low vacuum and atmospheric) and surface pretreatments. Mixed solution (H/sub 2/SO/sub 4/ and H/sub 2/O/sub 2/) standard cleaning, warm nitric acid and O/sub 2/-plasma-assisted surface pretreatments have been considered and compared. The void formation is clarified according to the void distribution and the measurement of surface energy. Long annealing time periods are considered in order to reach the saturation of the interface chemical reactions. Our experiments demonstrate that the origin of voids appearing in low temperature O/sub 2/-plasma-enhanced wafer bonding is related to the great quantity of chemical reaction products. It has been shown that optimized O/sub 2/-plasma pretreatment time can lead to void-free, uniform and high surface energy (over 2.0 J/m/sup 2/) wafer bonding. In the case of SiO/sub 2/-SiO/sub 2/ wafer bonding, our experimental results show that below a certain critical silicon dioxide thickness the reaction products cannot be absorbed totally and then voids occur. Presenting a higher surface energy than warm nitric acid O/sub 2/-plasma is an extremely promising surface pretreatment solution for the increasing demand of low-temperature wafer bonding techniques.     

Fabrication of a MEMS capacitive accelerometer with symmetrical double-sided serpentine beam-mass structure

This paper presents a symmetrical double-sided serpentine beam-mass structure design with a convenient and precise process of manufacturing MEMS accelerometers. The symmetrical double-sided serpentine beam-mass structure is fabricated from a single double-device-layer SOI wafer, which has identical buried oxides and device layers on both sides of a thick handle layer. The fabrication process produced proof mass with though wafer thickness (860 μm) to enable formation of a larger proof mass. Two layers of single crystal silicon serpentine beams with highly controllable dimension suspend the proof mass from both sides. A sandwich differential capacitive accelerometer based on symmetrical double-sided serpentine beams-mass structure is fabricated by three layer silicon/silicon wafer direct bonding. The resonance frequency of the accelerometer is measured in open loop system by a network analyzer. The quality factor and the resonant frequency are 14 and 724 Hz, respectively. The differential capacitance sensitivity of the fabricated accelerometer is 15 pF/g. The sensitivity of the device with close loop interface circuit is 2 V/g, and the nonlinearity is 0.6 % over the range of 0–1 g. The measured input referred noise floor of accelerometer with interface circuit is 2 μg/√Hz (0–250 Hz).     

A pendulous oscillating gyroscopic accelerometer fabricated using deep-reactive ion etching

A silicon pendulous oscillating gyroscopic accelerometer (POGA) was fabricated using deep-reactive ion etching (DRIE) and silicon wafer bonding technologies. A POGA is the micromachining-compatible analog of the pendulous integrating gyroscopic accelerometer (PIGA), which is the basis of the most sensitive accelerometers demonstrated to date. Gyroscopic accelerometers rely on the principle of rebalancing an acceleration-sensing pendulous mass by means of an induced gyroscopic torque. The accelerometer is composed of three individual layers that are assembled into the final instrument. The top layer uses wafer bonding of an oxidized wafer to a handling wafer to create a silicon-on-oxide wafer pair, in which the oxide layer provides electrical isolation between the mechanical members and the handling layer. The middle layer is a two-gimbal torsionally-supported silicon structure and is in turn supported by an underlying drive/sense layer. The micromachined POGA operated according to gyroscopic accelerometer principles, having better than milligram resolution and dynamic ranges in excess of 1 g (open loop) and approximately 12 mg (closed loop).     

Versatile low temperature wafer bonding and bond strength measurement by a blister test method

We present a low temperature plasma assisted bonding process that enables the bonding of silicon, silicon oxide and silicon nitride wafers among each other at annealing temperatures as low as room temperature. The process can be applied using standard clean room equipment. Surface energies of differently treated bonded samples are determined by a blister test method for square shaped cavities. For this reason, we extend the well-known blister test method for round shaped cavities to the square shaped case by a combined analytical and numerical approach. Accordingly, the energetic favored crack front propagation in the bond interface is determined by numerical simulations. The surface energies of the tested samples are calculated and compared to anodic silicon-to-Pyrex^® bonds. Surface energies of up to 2.6 J/m² can be achieved between silicon and silicon oxide wafer pairs at low annealing temperatures. Room temperature bonded samples show a surface energy of 1.9 J/m². The surface energy of silicon-to-Pyrex glass bonds yields 1.3 J/m². Small structures, e.g., bridges down to 5 μm can be bonded using the discussed bonding process. Selective bonding of silicon-to-silicon oxide wafer pairs is performed by structuring the oxide layer. The successful integration of the bonding process into the fabrication of micropumps is highlighted.     

Design and fabrication of silicon condenser microphone usingcorrugated diaphragm technique

A novel silicon condenser microphone with a corrugated diaphragm has been proposed, designed, fabricated and tested. The microphone is fabricated on a single wafer by use of silicon anisotropic etching and sacrificial layer etching techniques, so that no bonding techniques are required. The introduction of corrugations has greatly increased the mechanical sensitivities of the microphone diaphragms due to the reduction of the initial stress in the thin films, For the purpose of further decreasing the thin film stress, composite diaphragms consisting of multilayer (polySi/Si_xN_y/polySi) materials have been fabricated, reducing the initial stress to a much lower level of about 70 MPa in tension. Three types of corrugation placements and several corrugation depths in a diaphragm area of 1 mm² have been designed and fabricated. Microphones with flat frequency response between 100 Hz and 8~16 kHz and open-circuit sensitivities as high as 8.1~14.2 mV/Pa under the bias voltages of 10~25 V have been fabricated in a reproducible way. The experimental results proved that the corrugation technique is promising for silicon condenser microphone     

Femtosecond laser-induced silicon surface morphology in water confinement

This article investigates the use of femtosecond laser induced surface morphology on silicon wafer surface in water confinement. Unlike irradiation of silicon surfaces in the air, there are no laser induced periodic structures, but irregular roughness is formed when the silicon wafer is ablated under water. The unique discovery of a smoothly processed silicon surface in water confinement under certain laser parameter combinations may help improve laser direct micromachining surface quality in industrial applications.     

辅助电极型硅传感器的热力学分析与实验

首次用热力学分析了硅传感器的辅助电极与熔液中硅、氧和碳的反应方向与限度。讨论了局域)与熔液中硅活度(a[Si])的相关性;揭示了前人用辅助电极型硅传感器对高碳熔液测量平衡氧逸度(fO2时可能发生附反应,指出了有效测量范围;发现了Mg2SiO4(s)+MgO(s.s.)硅传感器存在测量盲区。研制了一种新Mg2SiO4(s)+MgO(s)硅传感器,用Mg2SiO4(s)+MgO(s)硅传感器测得了盲区内高碳低硅熔液中硅的活度,实验表明该测量无附反应发生,证明了热力学分析是可信的。     

Micro-mixer device with deep channels in silicon using modified RIE process: fabrication,packaging and characterization

In the present work, silicon based micromixer microfluidic devices have been fabricated in silicon substrates of 2-inch diameter. These devices are of 2-input and 1-output port configuration bearing channel depth in the range 80–280 µm. Conventional reactive ion etching (RIE) process used in integrated circuit fabrication was modified to get reasonably high silicon etch rate (~1.2 µm/min). It was anticipated that devices with channel depth in excess of 150 µm would become weak and susceptible to breakage. For such devices, a bonded pair of silicon having a 0.5 µm SiO₂ at the bonded interface was used as the starting substrate. The processed silicon wafer bearing channels was anodically bonded to a Corning^® 7740 glass plate of identical size for fluid confinement. Through-holes for input/output ports were made either in Si substrate or in glass plate before carrying out anodic bonding. Micro-channels were characterized using stylus and optical profiler. Surface roughness of the channel was observed to increase with increasing channel depth. The devices were packaged in a polycarbonate housing and pressure drop versus flow rate measurements were carried out. Reynolds number and friction factor were calculated for devices with 82 µm deep channels. It was observed that up to 25 sccm of gas and 10 ml/min of liquid, the flow was laminar in nature. It is envisaged that using bonded silicon wafer pair and combination of RIE and wet etching, it is possible to get an etch stop at the SiO₂ layer of the bonded silicon interface with much smaller value of surface roughness rendering smooth channel surface.