HybridTCache:一种基于专用事务Cache的软硬件协同事务内存系统

文中提出一种高效的软硬件协同事务内存系统HybridTCache.在通常情况下,事务完全由硬件执行,当事务大小超出了硬件限制时,操作系统将协同硬件执行.HybridTCache提出了一种新的专用事务Cache,称为TCache,缓存事务执行过程中的临时数据,由操作系统协同管理TCache溢出.文中给出了基于GEMS模拟器的HybridTCache原型系统.系统的评测显示HybridTCache比传统系统在性能、可扩展性、设计复杂度方面有较好的改进.     

JDBC事务操作探讨

文章详细阐述了JDBC事务操作的提交模式、回滚模式以及并发事务操作容易出现的诸多数据不一致的问题,分析了如何选择不同事务隔离级别,以在保持数据一致性的同时提高系统性能,最后以Oracle数据库为例,讨论了JDBC的实现细节和内部执行机制.     

面向数据中心的事务内存框架设计

针对由计算机集群构成的云计算数据中心的特性,提出了一种基于事务内存的分布式编程框架。该框架将云计算任务封装为事务,自动完成所有事务的调度执行、负载均衡和故障恢复;将数据中心的分布式数据封装为事务对象,保证事务访问事务对象时的ACID特性。与同类研究相比,它无需用户关心程序的并行控制,具有简单易用性。该框架已在仿真环境下实现,实验结果表明它具有良好的可扩展性和容错性。     

磐仪PICMG1．3单板电脑支持Intel第二代Corei系列处理器

磐仪科技推出PICMG1．3规格全长卡HiCORE—i67Q1,支持今年最新的第二代IntelCorei3／i5／i7处理器。其内建IntelQ67芯片组,具备Intel睿频加速、超线程及vPro等技术,不但提高执行效率,并针对系统安全与管理功能提供更多的硬件支持,搭载有两个DDR31066／1333内存插槽,可支持高...     

基于现代通用处理器的数据库优化综述

随着硬件技术的不断发展,计算机性能不断加强,数据库的性能也日益提高.但也造成了一些新问题,比如Cache延迟的加剧、Cache访问冲突等.针对这些新问题,按照各种优化技术的分类,深入分析了近10年来现代处理器用于数据库算法优化的各种研究成果,并展望了未来基于新硬件的数据库优化的发展趋势.     

集群上软件事务内存的层次化冲突检测

大多数事务内存研究都在多核处理器上进行,只有少数研究针对集群计算环境。现有的集群事务内存性能较差,因为事务内存的运行需要进行大量的远程内存访问,而集群的内存分布性使得远程内存访问的性能较差。事务内存运行中的冲突检测是进行远程内存访问最多的操作。我们提出了一种层次化的冲突检测方法,将其分为两个步骤进行,这种层次化的策略可以使集群上的软件事务内存获得高性能。     

基于快照机制的事务处理及其在RTDBS中的应用

为解决事务处理中的数据并发访问问题,该文提出了一种基于内存快照的加锁机制,并研究了这种机制在传统事务中的应用;此外,还探讨了快照机制在解决实时数据库系统的事务执行期限问题和全回卷问题等方面的应用。     

基于补偿操作的嵌套事务死锁处理方法

补偿操作是实现复杂的数据库应用环境中嵌套事务回滚的有效方法，但是基于封锁机制的补偿操作在执行时有可能导致不可补偿死锁．文中介绍了基于补偿操作的嵌套事务死锁处理方法，讨论了两种可避免不可补偿死锁产生的安全补偿方法，并比较了它们的特点．     

新型内存硬件环境中的事务管理系统综述

大数据爆发的时代产生了各种新的业务类型,业务数据驱动着事务管理系统创新性的迭代发展.由于传统持久化介质的制约,传统的事务管理系统无法高效执行事务.并且,解决事务冲突的额外开销仍然会限制事务管理系统的吞吐.新型硬件的商业化应用为事务管理系统注入了更多的可能性,在学术界和工业界均得到了广泛关注.硬件事务内存可以为事务管理系统提供硬件级别的事务冲突检测.而且,相对于固态硬盘,非易失性内存的字节寻址和持久化特性可以显著降低事务延迟并提升事务管理系统的性能.但是,现有的事务管理系统技术无法充分地利用硬件本身带来的性能提升,因此需要重构事务架构来解决这个问题.首先对新型硬件环境下的事务管理系统进行总结分析;之后总结了当前基于新型硬件事务管理系统的技术路线,明确了硬件事务内存和非易失性存储硬件下的事务管理系统的优势和不足;最后指明了新型硬件环境中事务管理系统未来可能的发展方向以及新的挑战.     

基于Snapshot加锁机制的事务模型的研究

为了解决事务中数据的并发访问问题,引入了各种加锁机制,在分析原有各种传统加锁协议的基础上,提出一种新的加锁机制,其于Snapshot 内存快照的加锁机制,并对它在单事务模型中的应用进行了研究和尝试。     

Atomic RMI: A Distributed Transactional Memory Framework

This paper presents Atomic RMI, a distributed transactional memory framework that supports the control flow model of execution. Atomic RMI extends Java RMI with distributed transactions that can run on many Java virtual machines located on different network nodes. Our system employs SVA, a fully-pessimistic concurrency control algorithm that provides exclusive access to shared objects and supports rollback and fault tolerance. SVA is capable of achieving a relatively high level of parallelism by interweaving transactions that access the same objects and by making transactions that do not share objects independent of one another. It also allows any operations within transactions, including irrevocable ones, like system calls, and provides an unobtrusive API. Our evaluation shows that in most cases Atomic RMI performs better than fine grained mutual-exclusion and read/write locking mechanisms. Atomic RMI also performs better than an optimistic transactional memory in environments with high contention and a high ratio of write operations, while being competitive otherwise.     

Transactional memory

Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.     

基于C#语言的事务内存系统

事务内存是一种新的易于使用的同步技术,能使多线程程序高效地并行执行,目前大多数事务内存系统都处于研究实验阶段,尚未具备实际应用价值,或需要依赖特殊硬件实现。针对该现状,提出一种利用C#语言设计与实现的纯软件的事务内存系统,包括事务对象定义以及对事务对象的并行访问方法,并给出处理事务冲突的策略。实验结果表明,该系统是一种高效简洁的同步实现机制。     

基于精化的可信执行环境内存隔离机制验证

可信执行环境(trusted execution environment, TEE)基于硬件隔离机制,为安全敏感应用提供隔离的执行环境,保护敏感数据的安全性.内存隔离机制是TEE的关键机制之一,用于对安全内存和非安全内存进行隔离,并对安全内存实施访问控制,如果其安全性不能保证,可能造成存储在安全内存中的敏感数据泄露.为验证TEE内存隔离机制的安全性,针对基于ARM TrustZone技术构建的TEE,提出一种基于精化的可信执行环境内存隔离机制安全性验证方法.建立抽象模型和具体模型,并定义两种模型之间的精化关系,在证明精化关系成立和抽象模型满足信息流安全性的前提下,验证具体模型的信息流安全性.具体模型建模了TEE内存隔离机制的关键硬件和软件,包括TrustZone地址空间控制器、MMU和TrustZone monitor等,在定理证明器Isabelle/HOL中,验证了该模型满足无干扰、无泄露、无影响等信息流安全属性.     

Transactional execution: toward reliable, high-performance multithreading

Although lock-based critical sections are the synchronization method of choice, they have significant performance limitations and lack certain properties, such as failure atomicity and stability. Addressing both these limitations requires considerable software overhead. Transactional lock removal can dynamically eliminate synchronization operations and achieve transparent transactional execution by treating lock-based critical sections as lock-free optimistic transactions.     

Data processing in the firmware systems for logic control based on search networks

It was proposed to use the hardware accelerators for analysis and data processing in the systems of logic control on a chip including the interacting processor system, memory, and configurable logic components. The data processing expected execution of operations over the sets of elements each of which can be activated by software and realized in the hardware in parallel networks admitting, if necessary, pipeline processing. New methods of design and use of the sorting and search networks were proposed, and the results of their theoretical and experimental comparison with the existing networks were presented.     

Efficient execution of speculative threads and transactions with hardware transactional memory

Thread-level speculation (TLS) was researched to automatically parallelize portions of serial programs for execution, and transactional memory (TM) was studied as a promising alternative of lock for parallel programming due to its simplicity. Both TLS and TM require similar underlying support. In the paper, we present SeTM (sequential transactional memory), a hardware enhanced TM system which supports TLS at minor extra cost. Signature is an effective way to buffer speculative states in TM and TLS. But it cripples TM and TLS performance due to its false-positive in terms of conflict detection, especially for conflict-intensive TLS. SeTM adopts R/W bits and signature concurrently to ameliorate this bad influence. Additionally, SeTM introduces the fast rollback mechanism, which provides fast abort recovery for eager log-based HTM and TLS. The most important contribution of SeTM is the conflict-tolerant mechanism, which tolerates some ambiguous data conflicts in TLS. Finally, in order to achieve an efficient execution for these un-order transactions, we add an extra ordering mechanism for SeTM. With this ordering mechanism, the transactions in TM can also gain the performance improvement with the support of conflict-tolerant mechanism. Our evaluation major on TM and TLS separately. For the TLS applications, six representative benchmarks have been adopted to evaluate the above model. Our experimental results show that our scheme improves the execution performance of most tested codes at a modest hardware cost. For a set of important scientific loops, we report the highest speedup of 6.5 with 15 cores. Besides, experimental results also show good scalability of SeTM system. For the TM applications, with respect to LogTM-SE, the benchmarks from STAMP also gain performance improvement signally.     

IMPULP: A Hardware Approach for In-Process Memory Protection via User-Level Partitioning

In recent years many security attacks occur when malicious codes abuse in-process memory resources.Due to the increasing complexity,an application program may call third-party code which cannot be controlled by programmers but may contain security vulnerabilities.As a result,the users have the risk of suffering information leakage and control flow hijacking.However,current solutions like Intel memory protection extensions(MPX)severely degrade performance,while other approaches like Intel memory protection keys(MPK)lack flexibility in dividing security domains.In this paper,we propose IMPULP,an effective and efficient hardware approach for in-process memory protection.The rationale of IMPULP is user-level partitioning that user code segments are divided into different security domains according to their instruction addresses,and accessible memory spaces are specified dynamically for each domain via a set of boundary registers.Each instruction related to memory access will be checked according to its security domain and the corresponding boundaries,and illegal in-process memory access of untrusted code segments will be prevented.IMPULP can be leveraged to prevent a wide range of in-process memory abuse attacks,such as buffer overflows and memory leakages.For verification,an FPGA prototype based on RISC-V instruction set architecture has been developed.We present eight tests to verify the effectiveness of IMPULP,including five memory protection function tests,a test to defense typical buffer overflow,a test to defense famous memory leakage attack named Heartbleed,and a test for security benchmark.We execute the SPEC CPU2006 benchmark programs to evaluate the efficiency of IMPULP.The performance overhead of IMPULP is less than 0.2%runtime on average,which is negligible.Moreover,the resource overhead is less than 5.5%for hardware modification of IMPULP.     

Hardware transactional memory: A high performance parallel programming model

The transactional memory in multicore processors has been a major research area over past several years. Many transactional memory systems have been proposed to be used to solve the synchronization problem of multicore processors. Hardware transactional memory is one of the critical methods to speedup communications in multicore environment. In this paper, we give a review of the current hardware transactional memory systems for multicore processors. We take a top-down approach to characterizing and classifying various hardware transactional design issues and present a taxonomy of hardware transactional memory systems which is consist of the five fundamental design issues: version management, conflict detection, contention management, virtualization and nesting. Finally, we discussed the active research challenge: the relationship between transactional memory and Input/Output operations and system calls.