嵌入式存储器的多故障自修复方法

使用冗余行覆盖占故障总数70%的单故障,导致冗余资源的浪费.为提高冗余资源的利用率,提出一种高效的修复方案,即冗余行覆盖多故障,纠错码修复单故障.当采用码率大于1/2的纠错码修复单故障时,校验住的长度小于冗余行的长度,节约了面积开销.通过2~4×8比特静态随机存取存储器(SRAM)的自修复实验,验证了新方案的可行性.实验结果表明,与冗余行结构相比,新的修复方案可以减小面积开销,提高芯片的最大工作频率.     

针对嵌入式Cache的内建自测试算法

通过分析嵌入式Cache存储器中使用的双端口字定向静态存储器(SRAM)和内容可寻址存储器(CAM)的功能故障模型,提出了有效地针对嵌入式应用的DS-MarchC E和DC—March CE测试算法,解决了以往算法用于嵌入式系统时故障覆盖率低或测试时间长导致测试效率低的问题．利用March CE算法并结合Cache系统的电路结构特点,设计并实现了一套集中管理的内建自测试测试方案．此方案可以并行测试Cache系统中不同容量、不同端口类型的存储器,并且能够测试地址变换表(TLB)的特殊结构,测试部分面积不到整个Cache系统的2％．     

SoC嵌入式存储器内建自修复方法

嵌入式存储器的内建自测试及修复是提高SoC芯片成品率的有效办法。详细描述了存储器良率的评估方法,提出了一种基于Mentor公司Tessent工具的存储器修复结构。该结构采用了冗余修复及电可编程熔丝eFuse硬修复的方法,具有很好的通用性及可行性,已多次应用在实际项目中。     

程序交换中存储故障校正系统

1.位交换容错技术 在交换机中存储器(RAM或ROM)是易出故障的部件。 位交换技术是将存储器中位的顺序重新排列完成的。在输出字的自动奇偶检测基础上,以程序自动判别故障位位置后,以冗余列代换故障列,既不需使用校正码,又不需作结构上的改变,就可显著地提高存储器的平均故障间隔时间MTBF,提高其可靠性。这种方法可扩充到多个冗余备用列,提高容错能力。对于只读存储器,将已查出的某位缺陷,以一个正确位(“0”或“1”),代替被阻断的差错位,达到校正的目的。     

一种嵌入式存储器内建自测试电路设计

随着存储器在芯片中变得越来越重要和半导体工艺到了深亚微米(deep-sub-micron,DSM)时代,对存储器的故障测试变得非常重要,存储器内建自测试(memory built—in self—test,MBIST)是一种有效测试嵌入式存储器的方法;给出了一种基于LFSR的存储器内建自测试电路设计,采用LFSR设计的地址生成器的面积开销相当小,从而大大降低了整个测试电路的硬件开销;16×32b SRAM内建自测试电路设计实验验证了此方法的可行性,与传统的方法相比,它具有面积开销小、工作速度快和故障覆盖率高等优点。     

R-RS:一种面向E级计算的内存可靠性增强技术

存储器可靠性问题是构建E级计算系统的关键挑战之一.存储器故障占计算机系统硬件故障的40%以上,随着存储器数量增加、存储器密度扩展和接口速率提升,E级计算机中存储器和访存传输通路的可靠性问题将会愈发严峻,传统的SEC-DED汉明码的纠检错能力难以满足E级系统高可靠性的需求.RS码是一种纠错能力很强的多项式编码,可实现Chipkill技术,然而,可纠多符号错的RS码的译码电路复杂,直接应用于存储器领域较为困难.本文提出了一种基于RS码和重传机制的内存可靠性增强技术——R-RS(Retransmission-RS),通过精心挑选本原多项式和校验矩阵设计了具有低硬件实现开销的RS编码,并通过精细化电路设计实现了并行高效低延迟译码,提出了基于窗口保序的重传机制对传输链路上的偶发故障所致错误进行重传,R-RS可纠正4个8位符号错,能够有效应对传输链路和存储器内部的随机单比特错、突发错以及传输链路偶发错误.R-RS的冗余存储开销为12.5%,性能开销是额外的1拍译码延迟,其面积仅占整个存储控制器的3.5%,与同类别的E-ECC方案相比,其纠正双颗粒、三颗粒突发错的能力分别提升了83.3%和109.5...     

基于SoC的嵌入式DRAM存储器内建自测试设计

内建自测试(Built-in Self Test,BIST)是测试片上系统(System on- Chip,SoC)中嵌入式存储器的重要技术;但是,利用BIST技术采用多种算法对嵌入式存储器进行测试仍面临诸多挑战;对此,提出了一种基于SoC的可以带有多种测试算法的嵌入式DRAM存储器BIST设计,所设计的测试电路可以复用状态机的状态,利用循环移位寄存器(Cyclic Shift Register,CSR)产生操作命令,利用地址产生电路产生所需地址;通过对3种BIST电路支持的算法,全速测试,面积开销3个方面的比较,表明提出的嵌入式DRAM存储器BIST设计在测试时间,测试故障覆盖率和测试面积开销等各方面都取得了较好的性能.     

一种容软错误的BIST结构

针对深亚微米工艺下瞬态故障引发的软错误可能成为芯片失效的重要原因,提出一种容软错误的BIST结构--FT-CBILBO.该结构对并发内建逻辑块观察器进行改进,通过对多输入特征寄存器进行功能复用,构建双模冗余的容错微结构,并且能有效地降低开销;在触发器输出端插入C单元,可有效地针对单事件翻转进行防护,阻塞瞬态故障引发的软错误.在UMC 0.18μm工艺下的实验结果表明,FT-CBILBO面积开销为28.37%～33.29%,性能开销为4.99%～18.20%.     

基于ECC校验码的存储器可扩展自修复算法设计

随着微电子工艺的不断进步,SoC芯片设计中SRAM所占面积越来越大,SRAM的缺陷率成为影响芯片成品率的重要因素。提出了一种可扩展的存储器自修复算法(S-MBISR),在对冗余的SRAM进行修复时,可扩展利用存储器访问通路中校验码的纠错能力,在不改变SRAM结构的前提下能够进一步提高存储器的容错能力,进而提高芯片成品率。最后对该算法进行了RTL设计实现。后端设计评估表明,该算法能够工作在1GHz频率,面积开销仅增加1.5%。     

基于EDAC的低开销星载迫零检测算法

针对基于传统三模冗余思想设计的星载MIMO检测算法中矩阵乘积运算资源占用率较高的问题,提出一种抗SEU的低开销星载EDAC迫零检测算法。通过在算法的矩阵乘积运算中扩展加入两行(列)"校验和",实现自检错、自纠错功能;采用模块化设计和乘法器核复用的方法,减少资源占用率和系统自恢复时间,整体提高系统的可靠性。仿真与测试结果表明,与基于三模冗余和RPR设计的迫零检测算法相比,该算法以较小的检错纠错延时为代价,提高了抗SEU性能,显著降低了资源占用率。     

Efficient Spare Allocation for Reconfigurable Arrays

Yield degradation from physical failures in large memories and processor arrays is of significant concern to semiconductor manufacturers. One method of increasing the yield for iterated arrays of memory cells or processing elements is to incorporate spare rows and columns in the die or wafer. These spare rows and columns can then be programmed into the array. The authors discuss the use of CAD approaches to reconfigure such arrays. The complexity of optimal reconfiguration is shown to be NP-complete. The authors present two algorithms for spare allocation that are based on graph-theoretic analysis. The first uses a branch-and-bound approach with early screening based on bipartite graph matching. The second is an efficient polynomial time-approximation algorithm. In contrast to existing greedy and exhaustive search algorithms, these algorithms provide highly efficient and flexible reconfiguration analysis.     

High-yield performance-efficient redundancy analysis for 2D memory

High-yield performance-efficient remapping architecture,repairing algorithms and redundancy analysis (HYPERA) are proposed for 2D memory.The proposed hypercube-based memory repair architecture consists of spare row-like subcubes with a modified ternary CAM with an address concentrator and a parallel sorter-like address concentrator.Generally,for an acceptable repair rate about 3% of spare subcubes and no more than 5% of hardware overhead are required. A modified Quine-McCluskey algorithm and the Essential C...     

PRIM: A Fast Matrix Transpose Method

An efficient algorithm called PRIM is proposed for transposing an arbitraxy R ×C matrix which is too large to be stored in its entirety in working memory and which instead is stored by rows on disk. PRIM facilitates the execution of numerical matrix algorithms which operate both by rows and by columns.     

Reconfigurable architecture for autonomous self-repair

Fault-tolerant systems typically require expensive additional resources (spare pins, columns, and chips) and external control for reconfiguration. We introduce an effective, low-cost repair solution in which originally unused blocks and routing resources replace faulty parts. In addition, the proposed reconfiguration hardware allows autonomous repair, that is, the system does not require external intervention for recovery.     

SIERRA—Simulation environment for memory redundancy algorithms

Extreme-scale computer systems take advantage of large arrays of general-purpose multicore processors coupled with specialized manycore accelerators. In order to support complex applications and correctly feed such processing elements, increasingly larger memory cores are integrated at different levels of the hierarchy. However, the adoption of increasingly aggressive manufacturing processes makes the memory sub-system particularly sensitive to faults. Error correcting codes (ECCs) allow the memory to recover from faults at run-time without interfering with the application execution. However, due to the loss of performance introduced every time an error must be corrected, the persistence of faults requires a more radical repair approach in which faulty cells are physically replaced by spare ones. Memory redundancy analysis (MRA) algorithms are used to drive the allocation process of spare resources. Many one-dimensional and two-dimensional MRAs have been proposed, but tools for evaluating their recovering capability are still not well established. This paper presents SIERRA, a simulation environment for precisely evaluating the repair efficiency of an MRA considering different fault signatures and faulty memory configurations. Our simulation engine provides a precise estimation of the MRA quality by analyzing the behavior of the MRA on several faulty memory configurations. To this end, different parameters such as the area of the memory blocks and the defect density are taken into account. The evaluation of the quality of an MRA takes into account its repairing capability, the power consumption derived from its execution, and the area overhead. Thanks to the use of a database for storing information, our tool is able to speed-up the simulation process by distributing it among several nodes. All these features make SIERRA essential in supporting the design of next-generation high-performance computers.     

跟踪机制引导的C程序内存错误自动修复

C语言执行效率高,使用范围广泛,然而存在的安全问题也日益突出。内存错误是C程序中常见的缺陷,严重时将导致系统崩溃。传统的人工修复内存错误耗费大量人力物力,并可能在修复过程中引入新的错误。针对这个问题,提出了一种基于跟踪机制的程序自动修复方法。构建包含程序文件中变量作用分布的作用域树;提出基于全局指针的跟踪机制,通过插入全局指针跟踪发生错误的分配内存在程序中的状态;基于全局指针自动生成补丁,利用作用域树定位缺陷修复位置从而来安全地修复内存错误。基于上述过程,实现了原型工具DTSFix,并在开源程序中对其进行了评估。实验结果表明,DTSFix能够有效检测并修复程序中的真实缺陷而且不产生副作用。     

Fast Co-Clustering by Ranking and Sampling

Co-clustering treats a data matrix in a symmetric fashion that a partitioning of rows can induce a partitioning of columns, and vice versa. It has been shown advantageous over tradition clustering. However, the computational complexity of most co-clustering algorithms are costly, and thus limit their e?ectiveness on large datasets. A recently proposed sampling-based matrix decomposition method can achieve a linear computational complexity, but selected rows and columns can not effectively represent a large sparse dataset, and many unselected rows and columns can not be mapped to the selected rows and columns because they do not share features in common, thus its performance is impaired. To address this problem, we propose a fast co-clustering framework by ranking and sampling that only representative samples are selected for co-clustering, and the remaining samples can be easily labeled by their neighbors in clustered samples. Extensive experiments on large text datasets show that our approach is able to use very few samples to achieve comparable results in linear time compared to state-of-the-art co-clustering algorithms of nonlinear computational complexity.     

高带宽远程内存结构中的预取研究

高速电路和光互联技术的发展极大地提高了网络的速度与带宽。因而,突破高性能计算机CPU与内存紧耦合的传统结构成为可能,CPU与内存的耦合不再受距离的限制,这必将引起体系结构的变革。文[1]提出DSAG结构——CPU与内存在空间上分离,每个CPU节点上仅留少量内存．将海量内存放在远程统一管理作为内存服务器,CPU节点和内存服务器之间通过高速网络互连。这种新的体系结构带来了更好的共享性和可扩展性,但同时也对我们解决CPU和内存之间的不平衡性问题带来了挑战。为了降低DSAG这种远程内存结构增加的访存时延,我们考虑到CPU正常访存没有充分利用网络的高带宽,因此可以利用剩余的网络带宽来进行远程内存数据的预取。本论文在应用程序执行时记录本地（相对于远程内存）不命中的地址信息,以页对齐分析其中存在的页框流（Page Frame Stream）的统计特征,并提出可基于页框流的预取机制可降低访存延迟、提升系统性能的观点。最后我们采用模拟的方法验证了观点的可行性与正确性,进一步提出了三种预取策略,比较并分析影响预取效果的因素。     

基于闪存的固态存储器的数据管理

提出了一种用于航天器的高速大容量固态存储器数据管理方案。存储器基于NAND型FLASH芯片，采用并行扩展及流水线操作的技术。向存储区加载一簇有效数据后，系统立即向每簇的空余区加载该簇的使用状态信息，保持了多簇数据连续写操作的流水线顺序，从而保证了系统的平均输入高速率。根据簇使用状态信息在内存中建立的簇分配表，系统实现对存储区高速灵活的管理。编程和擦除过程中新出现的无效块，将通过硬件电路自动标记并旁路。     

Optimal cutting design and analysis for fault-tolerant scheme of redundant memories

Fault-tolerant design for memory production is beginning to play an important role in increasing the yield rate of manufacturing. To improve the reliability of memory manufacturing, there are many methods that have been proposed. One of the most used technologies is replacing the faulty cells with spare memory interleaved in the memory. Nowadays, laser-cutting technology improves the yield of memories because of the enhancement of the use of spare lines. However, the issue of choosing a cutting location significantly affects the utilisation of spare lines. A bad cutting location can even render it useless. To use spare lines more efficiently, this article proposes two algorithms. The first one is designed to seek out a good cutting location. It corrects some defects of previous algorithms and provides a better approach to finding cutting candidates. In addition, because most heuristic solution-finding algorithms do not work properly under the condition of cutting memory, the second algorithm, called modification of most-repair is proposed to help make the decision as to whether or not a solution exists for the faulty pattern. We can find an optimal solution by combing these two algorithms. The experimental results show that our proposed algorithms increase the reparable percentage of a 1024-by-1024 memory from 55 to 100% and also improve both the reliability of memory manufacturing and the flexibility of spare lines.