共查询到20条相似文献,搜索用时 93 毫秒
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为了提高AES算法在硬件平台上的实现性能,通过对AES算法S盒构造原理进行分析,构造了一个新S盒。与AES算法的S盒相比,新S盒在硬件实现时将使用更少的硬件资源并具有更快的运行速度,因而更适合在低档硬件上实现。同时,分析并证明了新S盒不会影响修改后的AES算法的强度。 相似文献
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AES中S盒是一个非线性的字节代替变换,在AES算法中占有较大的比重,也是整个AES加解密硬件实现的关键模块.分析基于费马定理的正逆S盒算法原理及特点,使用Verilog HDL设计可逆S盒电路,通过FPGA实现正逆S盒运算.电路引入可装配的流水线结构,设计一种小规模、快速的可逆S盒运算电路,既可实现正S盒运算,又可实现逆S盒运算,加速S盒运算的过程,减小AES加解密电路的规模,对AES算法的硬件实现具有实际价值. 相似文献
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基于AES和DES算法的可重构S盒硬件实现 总被引:5,自引:0,他引:5
密码芯片的可重构性不仅可以提高安全性,而且可以提高芯片适应性.S盒是很多密码算法中的重要部件,其可重构性对密码芯片的可重构性有重大影响.文章在分析AES和DES算法中S盒硬件实现方法的基础上,利用硬件复用和重构的概念和相关技术,提出了一种可重构S盒(RC-S)结构及其实现方法.实验结果表明RC-S可用于AES算法和DES的硬件实现.基于RC-S的AES、DES密码模块规模分别是AES、DES模块的0.81/1.13,性能分别是DES/AES的0.79/0.94. 相似文献
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该文提出了一种基于随机掩码的抗DPA(Differential Power Analysis)攻击的AES算法硬件实现方案。基于随机掩码的AES算法实现中最为关键之处就是唯一的非线性变换即S盒(SubBytes)的实现,该文将S盒中有限域GF(28)上的求逆转换到GF(24)和GF(22)上进行,有效实现了掩码防护。在该文的实现中,所有的中间结果均被随机掩码,证明了该文中AES算法实现能够抗DPA攻击,基于此掩码方案,给出了AES协处理器体系结构,设计实现128密钥的AES协处理器。在0.18μm工艺下,协处理器面积为0.298mm2 在100MHz频率下,加解密吞吐率达到了1.16Gbps。 相似文献
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以AES加密算法作为基础,描述了一种适用于汽车RKE系统的单向消息认证码(MAC)协议,并且对AES的轮操作结构进行了优化设计,用查表算法代替乘法运算,使整个算法只需要用查表及加法两种操作就能实现。最后,以车身控制领域广泛使用的S12X单片机作为接收端载体,介绍了通过AES加密后的MAC码在双核构架上的高效实现方案。 相似文献
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陈作新 《电脑编程技巧与维护》2006,(7):20-25,38
Riindael作为美国高级加密标准算法,具备较好的可靠性和抗攻击能力,将代替DES在各领域得到广泛应用。文章详细分析了Rijndael主要运算部件S盒、逆S盒、列混合变换、逆列混合变换的基本原理和算法,并用Delphi语言编写出源代码。通过查表计算可以快速地、方便地实现AES加密算法和解密算法,因此.本文对于研究、分析和应用Rijndael算法具有重要意义。 相似文献
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Sheikh Muhammad Farhan Shoab A. Khan Habibullah Jamal 《Microprocessors and Microsystems》2009,33(3):221-231
The complexity involved in mapping an algorithm to hardware is a function of the controller logic and data path. Minimizing data path size can lead to significant savings in hardware area and power dissipation. This paper presents an implementation of a novel architectural transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. The technique divides the input word to several bytes and then traces each byte for extracting architectural transformation. The technique is applied on Advanced Encryption Standard (AES) algorithm which is non-linear in nature. Using this technique, the 32-bit AES algorithm is transformed into a byte-systolic architecture. The novelty of the technique is more pronounced around the mix column design which is the most complex part of the AES algorithm. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed to support 8-bit operations. The resulted AES architectures reuse same logic resources for key expansion and encryption/decryption. The proposed design offers moderate data rates in the range of 41 Mbps for encryption and 37 Mbps for decryption while utilizing 236 and 280 slices, respectively, on Xilinx Virtex II xc2v1000-6 FPGA. Comparison results show significant gain in throughput when compared with other 8-bit designs. This makes it a viable data/communication security solution for a variety of embedded and consumer electronics. 相似文献
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一种高吞吐率低成本的AES协处理器设计* 总被引:1,自引:0,他引:1
设计了一种高吞吐率低成本的AES协处理器。在加解密过程中采用共享技术,S盒采用复合域算法,减少了面积的需求;在轮内设计四级流水结构,有效地缩短关键路径,从而提高了处理器的数据吞吐率;同时在密钥扩展模块内插入寄存器,保证了轮密钥与轮循环的同步。基于Virtex II Pro FPGA 芯片(90 nm工艺技术)实现该结构,消耗面积仅约2 118 slices;在最高工作频率189 MHz下,128位加密的数据吞吐率达到1.8 Gbps。与同类设计相比,该处理器吞吐率/资源消耗比值较高。 相似文献
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Jaeik Cho Setiawan Soekamtoputra Ken Choi Jongsub Moon 《Computers & Mathematics with Applications》2013,65(9):1378-1383
Advanced Encryption Standard (AES) has replaced its predecessor, Double Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and power consumption due to more operations that need to be done. Some companies that employ ultra-high security in their systems may look for a key size bigger than 256-bit AES. In this paper, 128 and 256-bit AES hardware, as well as two variants of an AES encryption algorithm for 512-bit and 1024-bit key size, are implemented and compared in terms of power consumption and area. The experiment is done in 45 nm CMOS technology at 1.1 V using a Synopys DC Compiler and Modelsim and total power consumption and area results are presented and graphically compared. 相似文献
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研究了AES分组密码对差分故障攻击的安全性,攻击采用面向字节的随机故障模型,结合差分分析技术,通过在AES第8轮列混淆操作前导入随机单字节故障,一次故障导入可将AES密钥搜索空间由2128降低到232.3,在93.6%的概率下,两次故障导入无需暴力破解可直接恢复128位AES密钥.数学分析和实验结果表明:分组密码差分S盒取值的不完全覆盖性为差分故障分析提供了可能性,而AES密码列混淆操作良好的扩散特性极大的提高了密钥恢复效率,另外,本文提出的故障分析模型可适用于其它使用S盒的分组密码算法. 相似文献
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A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Uroš LegatAuthor Vitae Anton Biasizzo Author VitaeFranc Novak Author Vitae 《Microprocessors and Microsystems》2011,35(4):405-416
This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process. The developed solution has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead. 相似文献