差分编码实现通用I/O口串行异步通信的方法

针对微处理器片上串行异步通信接口灵活性欠佳的不足,给出了一种将微处理器通用I/O口扩展成串行异步通信口的方法。利用微处理器自身的定时器,结合有限状态机设计思想,采用差分编码原理在通用I/O口实现了串行异步通信,该方法可以灵活地设定通信帧格式与码元长度。通过示波器检测发送端口的波形,验证了此方法的可行性,在解决通信可靠性和稳定性的同时,为微处理器串行接口的扩展和非标准协议串行通信提供了一种方案,简化了传统串行通信端口的扩展方法。     

Parallel I/O options for 8085-based systems

Realtime applications of any microprocessor necessitate interfacing to a large variety of peripheral devices. Various interfacing techniques are discussed. Examples are given in which Intel's 8085 is taken as the typical microprocessor. The I/O transfers considered fall into two categories: memory-mapped transfers and I/O-mapped transfers. Both synchronous and asynchronous types are dealt with. Bit masking and interrupt techniques were used for asynchronous memory-mapped I/O transfer.Also included are multiplexed channel transfers and interrupt transfers. The former are treated as a special class of I/O transfer. The latter are useful in applications where it cannot be predicted when data will arrive for transfer to the microprocessor. Unlike other types of transfer, interrupt transfers are initiated by the I/O devices and not by the microprocessor. They are subdivided into software- and hardware-polled transfers. Examples are given of daisychain and search ring transfers.     

Area I/O's potential for future processor systems

Bandwidth, latency, system speed, and, of course, the size of future microprocessor systems all highly depend on interconnection technologies. Interconnection will become the key performance bottleneck as semiconductor technology improvements continue to reduce feature size. In this article, we describe the use of on-chip area I/O for future microprocessor systems on the basis of a case study we made of an Intel Pentium system. Area I/O is simply a method of locating I/Os over the entire chip instead of just the periphery. We show that system designers can achieve significant performance gains with area I/O and size reductions at both the system and chip levels. We also explain how area I/O in conjunction with high-density interconnects leads to a new package and chip partitioning concept     

Supply facility and input/output point locations in the presence of barriers

This paper studies a facility location model in which two-dimensional Euclidean space represents the layout of a shop floor. The demand is generated by fixed rectangular-shaped user sites and served by a single supply facility. It is assumed that (i) communication between the supply point and a demand facility occurs at an input/output (I/O) point on the demand facility itself, (ii) the facilities themselves pose barriers to travel and (iii) distance measurement is as per the L₁-metric. The objective is to determine optimal locations of the supply facility as well as I/O points on the demand facilities, in order to minimize total transportation costs. Several, increasingly more complex, versions of the model are formulated and polynomial time algorithms are developed to find the optimal locations in each case.Scope and purposeIn a facility layout setting, often a new central supply facility such as a parts supply center or tool crib needs to be located to serve the existing demand facilities (e.g., workstations or maintenance areas). The demand facilities are physical entities that occupy space, that cannot be traveled through, and that receive material from the central facility, through a perimeter I/O (input/output or drop-off/pick-up) point. This paper addresses the joint problem of locating the central facility and determining the I/O point on each demand facility to minimize the total material transportation cost. Different versions of this problem are considered. The solution methods draw from and extend results of location theory for a class of restricted location problems. For practitioners, simple results and polynomial time algorithms are developed for solving these facility (re) design problems.     

Tools and techniques for teaching microprocessor software development

Debugging low level language software can be a difficult business—the bare microprocessor lacks the user interface; facilities, such as simulators, provided on another machine can be tedious to use on running or partially working programs. A resolution of this difficulty lies in the harmonious use of a mainframe-based debugging system and a real microprocessor. This paper describes tools and techniques for the development of low level software for the Intel 8080 microprocessor employing both simulated and real microprocessors. The debugging system allows the user to set up a virtual microprocessor into which programs can be loaded and run and from which a flexible tracing of the executing program can be obtained. The debugging system is built into a general purpose multi-access operating system and this approach makes it possible to provide the system cheaply to a large number of users. Additionally, users have access to all the general facilities (such as editors) provided by the operating system itself. The system has been implemented on a minicomputer with 60 VDU terminals all of which can be used for interaction with the 8080 simulator or for general interactions with the mainframe operating system. The system has also been implemented in a self-simulating version to run on a real Intel 8080 microprocessor. Many of the VDUs on the minicomputer are controlled by Intel 8080 microprocessors and it is possible to load and run large Intel 8080 programs which were assembled (and tested) on the mainframe or run the self simulator based debugging system. In this way a range of complementary debugging environments is provided: the simulator on the mainframe with its access to backing store (and, hence, the ability to save trace information), the self simulator on the microprocessor (with its better performance for the single user), and the actual Intel 8080 itself. The user can easily move a partially tested program between environments and thus use the environment which best suits his current phase of testing.     

MUMS–A Reconfigurable Microprocessor Architecture

The would-be microprocessor user is currently confronted with a large and increasing number of different devices, each characterized by a unique architecture, instruction set, and hardware conventions, and provided with a varying, usually small degree of software support. Consequently, microprocessor systems reflect to a major extent the hardware and software idiosyncracies of the specific microprocessor(s) they incorporate; any attempt to replace a microprocessor with a newer or improved type, however inexpensive, entails a major system redesign. The work described in this article–MUMS, for Modular-Unified-Microprocessor-System–is an ongoing research project to overcome these limitations, having a modular, standardized, and versatile structure that is nevertheless commensurate with the low cost of the microprocessors themselves. Basic to this idea is a relatively simple micro-bus (the MUMS bus) that carries generic signals only, and over which a microprocessor communicates with its environment. Each microprocessor and all other modules, whether memory or I/O devices, connect to the MUMS bus through simple interfaces that standardize to the bus protocol. Simplicity is retained by having one microprocessor per MUMS bus, but flexibility is provided by allowing for MUMS busses to connect through a communications unit for the purpose of interprocessor communication or shared resources, or both. By this technique MUMS can be used in a standalone configuration or in conjunction with other processors. The insertion of a new nicroprocessor requires only one new MUMS bus interface and an associated software utility package in a ROM module; the rest of the system is unmodified.     

Book Review

Floppy Disk Drive: FD360 micro-peripheral floppy disk drive operates under directions from Intel or National Semiconductor microprocessor system. Hardware interfaces and FDOS (Floppy Disk Operating Systems) available for Intellec-8, Intellec-8/Mod-80, IMP-16P, 16L, 8P. Features include format compatibility with IBM 3741, 3742, 3540 systems, built-in hardware track seek and seek verification, automatic head load/unload load, operation with programmed I/O or DMA interfaces, sector buffering to enable asynchronous programmed I/O. Eight input, 16 output lines provide interfacing. Single drive configuration, $2350 (unit); 2 drives, $3000. Special interfaces available. – iCOM, Canoga Park, CA.     

Microprocessor Input/Output Architecture

There are at least as many different microprocessor input/output organizations, circuit configurations, and device types as there are microprocessor families and manufacturers. Due to the diversity of competing approaches and devices, their similarities and differences are not always evident. The fact that each manufacturer describes his approaches and devices differently, and the relative scarcity of formal text material on microprocessors, do not make the situation any better. In this short space there is no hope of comprehensively surveying all available approaches and devices (nor would I want to, even if space were available!). On the other hand, I can present an overview of basic microprocessor I/O organization and typical circuit configurations and devices. Using these concepts as a basis, one may be able to make comparisons between current and future approaches available commercially.     

Product Profile

Floppy Disk Drive: FD360 micro-peripheral floppy disk drive operates under directions from Intel or National Semiconductor microprocessor system. Hardware interfaces and FDOS (Floppy Disk Operating Systems) available for Intellec-8, Intellec-8/Mod-80, IMP-16P, 16L, 8P. Features include format compatibility with IBM 3741, 3742, 3540 systems, built-in hardware track seek and seek verification, automatic head load/unload, operation with programmed I/O or DMA interfaces, sector buffering to enable asynchronous programmed I/O. Eight input, 16 output lines provide interfacing. Single drive configuration, $2350 (unit); 2 drives, $3000. Special interfaces available. – iCOM, Canoga Park, CA.     

Microprogrammable peripheral controller

One of the most talked about microprocessor applications in the computer peripheral industry is device control. This paper presents a microsequencer-based general-purpose microprogrammable peripheral controller. This controller enables efficient and easy coupling between a wide range of I/O buses and peripherals. As an example, design details are given for interfacing a card reader onto an IBM standard I/O bus.     

列车固体录音装置的音频系统设计与实现

针对列车固体录音装置对无线电台通话录音的要求,介绍了由AT91SAM9261微处理器与UDA1341TS音频处理芯片组成的基于嵌入式Linux的音频系统的构建;提出了音频系统的软硬件设计方案,利用微处理器的同步串行控制器(SSC)和通用I/O口实现了音频数据及控制信号的传输;在驱动程序设计中采用DMA传输方式,并且使用缓存分段技术对DMA缓存区的管理方式进行了改进,使得对音频数据的处理速度有了较大提高,保证了系统的实时性要求;该系统已经成功地对列车无线列调电台之间的通话进行了录音测试,达到了较好的录放音效果.     

通信处理器的Boot Loader及I/O接口驱动程序

针对Ethernet/IP通信处理器的开发,采用S3C2410 ARM9微处理器和Windows CE.NET嵌入式操作系统,建立了通信处理器的Boot Loader和I/O接口驱动程序。Boot Loader与硬件高度相关,担负着初始化系统硬件和引导操作系统的双重任务。而I/O接口驱动程序使操作系统自动识别外围数据采集设备,为应用程序对底层设备的操控提供服务。实验测试表明该Ethernet/IP通信处理器运行稳定、可靠。     

基于ARM9的嵌入式pH值测控系统设计

本文介绍了一种基于ARM9微处理器S3C2410A的嵌入式pH值测控系统,包括S3C2410A自带的A/D转换器ADC,D/A转换芯片DAC8420等接口芯片的软硬件设计。利用微处理器S3C2410A丰富的I/O接口,通过74LS245电平转换芯片,解决了S3C2410A嵌入式处理器I/O接口输出电平与外设驱动电平不匹配的问题。     

CANOpen总线与软PLC在MPS中的应用

针对MPS系统I/O多、分散广、实时性和可靠性要求高等特点,设计了一种基于C8051F040的现场总线分布式控制系统。应用C8051F040单片机开发了基于CANopen协议的I/O从站,本文介绍了从站的硬件设计和软件设计。通过上位机CAN卡构建了基于CoDeSys软PLC的分布式I/O控制系统。给出了该系统在MPS中的调试过程。经系统测试和模拟运行表明,I/O从站与监控主机通讯可靠、准确,实时性满足了MPS控制系统的要求,具有一定的参考价值和广阔的应用前景。     

基于CANOpen协议的I/O从站的开发与应用

CANopen作为CAN总线的一种很有影响力的应用层协议,在工厂自动化系统中得到广泛应用。软PLC是一种基于PC机的新兴自动控制技术,不仅能够实现硬PLC的所有功能,而且遵循IEC61131-3编程标准,为用户提供了更多的开放性。本文应用P87C591单片机开发了基于CANopen协议的I/O从站,通过上位机CAN卡构建了基于CoDeSys软PLC的分布式I/O控制系统,验证了系统信息传递的可靠性、准确性和实时性,很好地满足了印刷机无轴传动控制系统的要求。     

基于ARM技术的电站仿真机接口系统的开发

为了改善基于串行总线技术的电站仿真机接口系统通信速率低、分布距离有限、扩展不方便以及调试困难,提出了基于ARM技术和以太网技术的分布式智能化输入输出接口系统.基于提出的分布式仿真机接口系统思想,分别从系统设计、系统软硬实现以及组态设计等进行了设计和实现.系统实际应用表明,基于ARM技术和以太网技术的接口系统通信速率高、分布距离远和扩展更方便,能够满足电站全范围仿真机输入输出接口的需要.     

Software development tool for target systems and EPROM programmers within a Unix environment

A computer running under a Unix operating system is an excellent host on which to develop software for target systems which have the same type of microprocessor as the host computer. Unfortunately, facilities for preparing executable modules able to be sent to an EPROM programmer or to be loaded onto a RAM portion of target memory space are lacking in standard Unix. These facilities can be improved in any version of Unix without the need for expensive software using the set of commands presented in this paper.     

Communication between two microprocessors through common memory

Advances in integration have enabled the design of dual microprocessor systems on a single board for extra processing power. The problems of interfacing these processors are discussed and reasons for preferring shared memory communications rather than I/O are outlined. A system using two 6809 microprocessors is described with the technical problems that were encountered or anticipated in its design. Software developed uses the ‘producer consumer’ analogy and three solutions are demonstrated.     

嵌入式远程I/O数据采集器的设计与实现

在电力、冶金等行业,目前传统的方式是将现场传感器输出的电阻、电流等信号用导线传送到控制室供二次仪表显示或计算机数据采集。采用LPC2134嵌入式ARM微处理器、A/D转换等集成电路并编制系统软件,设计了新型的嵌入式远程I/O数据采集器。该采集器可以在传感器附近就地安装,通过双绞线相联组成分布式测量系统。大量现场运用表明,由于该数据采集器测量数据是通过数字量远程传输,因此具有抗干扰能力强、测量精度高等优点,大大节约了信号电缆以及工程安装费用。     

New Products

The Model 121 "Naked" Floppy Disk Controller is a multipurpose, multi-drive floppy disk memory device aimed at both microprocessor and minicomputer applications. According to the manufacturer, the unit is compatible with DMA channels as well as programmed I/O channels, interfaces with most minicomputers and microprocessors, and can be made software-compatible with existing disk systems.