The AB‐C Doherty power amplifier. Part II: Validation

In part I, the complete theoretical (and nonlinear) analysis of a Doherty amplifier employing a Class AB bias condition for the Main Amplifier and a Class C one for the Auxiliary device has been presented. In this article, the experimental validation of the proposed theory is presented, describing the step‐by‐step procedure to be adopted when designing an AB‐C Doherty. The amplifier was realized at 2.14 GHz in hybrid form using two (0.5 μm, 1 mm gate periphery) GaN HEMTs. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

一种高线性度AB类CMOS功率放大器的设计与实现

率放大器作为发射机中最核心的模块之一,如何同时提高其效率和线性度一直是人们研究的热点。文章主要分析了AB类功率放大器中的主要非线性源—栅源电容对电路性能的影响,并且使用了一个PMOS管并联的技术来补偿这种影响,最后利用这种技术,采用JAZZ0.25um RF CMOS工艺实现了一个可应用于2.45GHz WLAN的高效率高线性度的AB类功率放大器,三阶交调(IM3)项为-12dBm,输出功率为26dBm,功率附加效率(PAE)为44%。     

A highly efficient PA design for WiMAX applications: Theory and experiment

Efficiency in microwave power amplifiers (PAs) is limited by the active device parameters and operating conditions. High values can be obtained by a proper selection of bias point and harmonic terminations or, from a different point of view, by a proper output voltage and/or current waveform shaping. This work outlines the mathematical statements for the proper design of a second harmonic tuning (HT) PA. To validate the theory, the design of a highly efficient 3.5 (WiMAX applications) GHz GaN HEMT PA based on second HT is presented. The measured performances confirm the improvement obtained by means of harmonic manipulation over Class AB tuned load or Class J PAs. An output power of 35.3 dBm has been measured for a maximum of power‐added efficiency of around 58% (drain efficiency 69.2%) with a IMD₃ of 19.1 dBc. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010.     

The large world of FET small‐signal equivalent circuits (invited paper)

The small‐signal equivalent circuit modeling of microwave field‐effect transistors (FETs) is an evergreen and ever flourishing research field that has to be up‐to‐date with technological developments. Hence, modeling techniques must be continuously adapted and extended to suit best evolving technologies. The extraction of a FET high‐frequency small‐signal equivalent circuit is a very active and broad research area of significant interest, owing to its use as a prerequisite for noise and large‐signal modeling. The aim of this invited article is to provide in‐depth knowledge, critical understanding, and new insights into how to extract a FET small‐signal equivalent circuit from both theoretical and practical perspectives. To illustrate potential solutions to the key challenges faced by researchers, experimental results for different semiconductor technologies are reported and discussed. The study is focused on the hot research topic of the cold approach that has been, and still is, the most widely used technique for extracting FET small‐signal models and on the active role of the transconductance for successful modeling. © 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2016.     

Broadband high‐efficiency monolithic InGaP/GaAs HBT power amplifiers for wireless applications

In this article, a broadband approach to high‐efficiency power amplifier performance, based on the parallel‐circuit Class E mode, is discussed. Results for a practical implementation of multi‐band and multi‐mode handset power amplifiers are shown. Measurements demonstrate the feasibility of the concept for highly efficient operation of DCS1800, PCS1900, CDMA2000, and WCDMA. PAE is greater than 50% at 30 dBm output power in the DCS1800 and PCS1900 bands, as well as better than 38% at 27 dBm output power and an ACLR of ?37 dBc is achieved for WCDMA operation. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 13, 496–510, 2003.     

Amorphous‐silicon gate‐driver circuits of shared‐node dual pull‐down structure with overlapped output signals

Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.     

电容式压力传感器微电容测量集成电路的研制

采用开关电容技术的Boxcar(时域平均)积分原理设计,为测量电容式压力传感器的微电容的接口电路已提出。它由Boxcar积分器,锁存器,脉冲宽度调制器和控制信号电路组成。该接口电路,采用3μm P-阱CMOS双层多晶硅栅工艺研制,管芯面积为2.5mm×3.5mm.测试结果表明,接口电路具有较好的灵敏度,它能将硅集成电容式压力(加速度)传感器集成在同一芯片上,实现一体化。     

Genetic algorithm‐based neural‐network modeling approach applied to AlGaN/GaN devices

An accurate equivalent circuit large‐signal model (ECLSM) for AlGaN‐GaN high electron mobility transistor (HEMT) is presented. The model is derived from a distributed small‐signal model that efficiently describes the physics of the device. A genetic neural‐network‐based model for the gate and drain currents and charges is presented along with its parameters extraction procedure. This model is embedded in the ECLSM, which is then implemented in CAD software and validated by pulsed and continuous large‐signal measurements of on‐wafer 8 × 125‐μm GaN on SiC substrate HEMT. Pulsed IV simulations show that the model can efficiently describe the bias dependency of trapping and self‐heating effects. Single‐ and two‐tone simulation results show that the model can accurately predict the output power and its harmonics and the associated intermodulation distortion (IMD) under different input‐power and bias conditions. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.     

A compact wideband balun design using double‐sided parallel strip lines with over 9:1 bandwidth

A simplified miniaturized wideband balun design covering (0.38‐3.5 GHz) is presented. The broadband balun structure occupies a small area of 20.7 mm × 20.8 mm. The balun is designed using low loss double‐sided parallel strip lines and is comprised of a two‐stage Wilkinson divider followed by loading, symmetrically, the two output ports. One port with a phase inverter circuit; while a very similar but non‐inverting circuit is placed in the other port for loading‐balance compensation. To realize the balun's function, different smooth transitions have been employed and were accounted for. The fabricated balun circuit demonstrated phase and amplitude imbalance of less than ±5° and ± 0.4 dB, respectively, over the band.     

Design scheme for broadband Doherty power amplifier using broadband load combiner

This article proposes a design strategy for broadband Doherty power amplifier (PA) using broadband load combiner. The bandwidth of the Doherty PA based on the proposed combiner using packaged transistor is about 2.5 times the bandwidth of conventional Doherty PA using a quarter‐wave transformer. An easy to implement analytical design methodology has been presented for the proposed load‐combiner while describing the bandwidth enhancement strategy. The design methodology is validated with the design of a broadband Doherty PA based on CREE 10 W packaged GaN high electron mobility transistor devices using the proposed load combiner. Measurement results show more than 45% drain efficiency at 6 dB output power back‐off (OPBO) over 400 MHz frequency range, centred around 1.95 GHz. The peak drain efficiency at saturation is better than 60% over this band of operation. At 6 dB OPBO, the maximum improvement of 18.5% in drain efficiency is achieved as compared to the balanced mode PA. Measurement with single carrier wideband code division multiple access modulated signal shows the average drain efficiency of more than 44% at 36.6 dBm average output power at center frequency of operation. The adjacent channel power ratio is better than ?45 dBc after applying digital predistortion. The circuit is realized with microstrip technology, which can be easily fabricated using conventional printed circuit processes. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:655–674, 2015.     

The AB‐C Doherty power amplifier. Part I: Theory

In this article, the complete theoretical analysis of a Doherty amplifier employing a Class AB bias condition for the Main and a Class C one for the Auxiliary devices, respectively, is presented. Starting from the simplified model of an active device, the analysis of the AB‐C Doherty behavior is carried out as a function of the input signal. In particular, the proposed approach is based on the analysis of the output drain current waveforms generated by the two active devices, while assuming a Tuned Load configuration (i.e., short circuit condition) for higher harmonic terminations. A closed form formulation is derived in order to directly design an AB‐C Doherty amplifier, while fully understanding the basis of its physical behavior. Finally, which Doherty parameters can be chosen by the designer or have to be implicitly fixed are discussed and clarified. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Basker: Parallel sparse LU factorization utilizing hierarchical parallelism and data layouts

Transient simulation in circuit simulation tools, such as SPICE and Xyce, depend on scalable and robust sparse LU factorizations for efficient numerical simulation of circuits and power grids. As the need for simulations of very large circuits grow, the prevalence of multicore architectures enable us to use shared memory parallel algorithms for such simulations. A parallel factorization is a critical component of such shared memory parallel simulations. We develop a parallel sparse factorization algorithm that can solve problems from circuit simulations efficiently, and map well to architectural features. This new factorization algorithm exposes hierarchical parallelism to accommodate irregular structure that arise in our target problems. It also uses a hierarchical two-dimensional data layout which reduces synchronization costs and maps to memory hierarchy found in multicore processors. We present an OpenMP based implementation of the parallel algorithm in a new multithreaded solver called Basker in the Trilinos framework. We present performance evaluations of Basker on the Intel SandyBridge and Xeon Phi platforms using circuit and power grid matrices taken from the University of Florida sparse matrix collection and from Xyce circuit simulation. Basker achieves a geometric mean speedup of 5.91× on CPU (16 cores) and 7.4× on Xeon Phi (32 cores) relative to state-of-the-art solver KLU. Basker outperforms Intel MKL Pardiso solver (PMKL) by as much as 30× on CPU (16 cores) and 7.5× on Xeon Phi (32 cores) for low fill-in circuit matrices. Furthermore, Basker provides 5.4× speedup on a challenging matrix sequence taken from an actual Xyce simulation.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

Analysis of response mechanism of a proton-pumping gate FET hydrogen gas sensor in air

Two different types of hydrogen response signals (DC and AC) of a proton-pumping gate FET with triple layer gate structure (Pd/proton conducting polymer/Pt) were obtained. The proton-pumping gate FET showed good selectivity against other gases (CH₄, C₂H₆, NH₃, and O₂). For practical use, the hydrogen response characteristics of the proton-pumping gate FET were investigated in air (a gaseous mixture of oxygen and nitrogen). The proton-pumping gate FET showed different hydrogen response characteristics in nitrogen as well as in air, despite the lack of oxygen interference independently. To clarify the response mechanism of the proton-pumping gate FET, a hydrogen response measurement was performed, using a gas flow system and electrochemical impedance spectroscopy. Consequently, the difference in response between nitrogen and air was found to be due to the hydrogen dissociation reaction and the interference with the proton transfer caused by the adsorbed oxygen on the upper Pd gate electrode.     

Microwave noise modeling for PHEMT using artificial neural network technique

An improved noise model for pseudomorphic high electron mobility transistors (PHEMT) based on the combination of the artificial neural network (ANN) and conventional equivalent circuit modeling technique is presented. The frequency dispersion of the gate noise model parameter P, drain noise model parameter R, and the correlation coefficient C have been taken into account by using an ANN model. The influence of the gate leakage current can be accommodated by using the proposed noise model. The noise model parameters are determined directly from on wafer noise parameters measurement based on the noise correlation matrix technique. Good prediction for noise parameters and significant improvements of the accuracy of noise parameters are obtained up to 26 GHz for 2 × 40 μm gate width (number of gate fingers × unit gate width) 0.25 μm Double Heterojunction δ‐doped PHEMTs over a wide range of bias points. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2–5.4 GHz, ?Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high‐speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post‐layout simulation results, phase noise is ?110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and ?113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation‐mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm² on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

10-26GHz CMOS六位数控衰减器设计与实现

为了使衰减器更好的适应相控阵系统对高集成度波束赋形电路的应用需求。基于55nm CMOS工艺,设计了一款具有低插入损耗、低附加相移特性的六位数控衰减器,该数控衰减器采用桥T和π型衰减结构级联而成,在10-26 GHz频率范围内实现步进为0.5dB、动态范围为0-31.5 dB的信号幅度衰减。为减小插入损耗,NMOS开关采用悬浮栅和悬浮衬底连接方式,同时采用了电容补偿网络和电感补偿以有效降低附加相移。仿真结果表明,在10-26GHz的频带范围内,该数控衰减器的插入损耗小于-7dB,输入/输出回波小于-10dB,附加相移小于±3°,所有衰减态的衰减误差均方根小于0.8dB,芯片的核心电路面积为0.36 mm×0.16 mm。     

Bezel free design of organic light emitting diode display via a‐InGaZnO gate driver circuit integration within active array

In this article, we described an innovative design technology of active matrix organic light emitting diode (AMOLED) display, to provide a bezel free design. We designed gate driver circuit of amorphous indium‐gallium‐zinc oxide thin‐film transistors (TFTs) not on the bezel area but within the active array. Although we applied challengeable design, no degradation of electrical/optical properties of panel was observed. Because we effectively prevented capacitive coupling and interference between the emission circuit and integrated gate driver circuit in active array, finally, we successfully demonstrated a bezel free designed AMOLED display of 18.3″ HD (1366 × 768) driven by a‐InGaZnO TFTs.     

磁轴承系统中差动变压器式位移传感器的研究

设计了用于磁悬浮轴承系统中的差动变压器式位移传感器。从基本原理出发,结合磁轴承特点,提出了改进的传感器结构方案。利用线性差动变压器的专用芯片AD598作为传感器的测量电路。实验结果表明:所设计的传感器具有较好的性能:在-0.35~0.35mm测量范围内,线性度为±1.25%,灵敏度可高达23.77mV/μm,完全适用于磁悬浮轴承系统中。     

Enhancement of Johnson figure of merit in III‐V HEMT combined with discrete field plate and AlGaN blocking layer

The performance of AlGaN/GaN HEMT is enhanced by using discrete field plate (DFP) and AlGaN blocking layer. The AlGaN blocking layer provides an excellent confinement of electrons toward the GaN channel, resulting very low subthreshold drain current of 10^?8 A/mm. It reveals very high off state breakdown voltage (BV) of 342 V for 250 nm gate technology HEMT. The breakdown voltage achieved for the proposed HEMT is 23% higher when compared to the breakdown voltage of conventional field plate HEMT device. In addition, the DFP reduces the gate capacitance (C_G) from 12.04 × 10^?13 to 10.48 × 10^?13 F/mm. Furthermore, the drain current and transconductance (g_m) reported for the proposed HEMT device are 0.82 A/mm and 314 mS/mm, respectively. Besides, the cut‐off frequency (f_T) exhibited for the proposed HEMT is 28 GHz. Moreover, the proposed HEMT records the highest Johnson figure of merit (JFOM) of 9.57 THz‐V for 250 nm gate technology without incorporating T‐gate.