一种基于单CPU单ASIC结构的软硬件划分算法

软硬件划分是软硬件协同设计中的关键问题之一。本文针对单CPU单ASIC结构嵌入式系统，提出了一种基于数据流图的划分算法。实验结果表明，该算法可以有效地解决软硬件划分问题，效率较高，对固定时间约束下硬件面积最小划分问题具有一定的实际意义。     

基于移动嵌入式系统硬/软件协同设计的EHSC算法

嵌入式系统设计的一个重要任务就是寻找硬/软件最佳搭配方案.随着系统复杂性的不断提高,采用嵌入式系统硬/软件协同设计是提高设计质量的有效手段.本文在讨论嵌入式系统设计一般方法的基础上,阐述了系统的硬/软件协同设计技术和硬件/软件划分方法,提出了以系统硬/软件划分策略为基础,系统组件的权重值为参考,组成元素划分为依据的设计理念,构造了基于移动环境的系统的硬/软件协同设计的EHSC（Embedded Hardware/Softwarre Codesign）模型.并依照此模型,实现了一种移动嵌入式系统“电子书包”阅读器的设计和开发.     

三种软硬件划分算法的比较分析

软硬件划分是嵌入式系统软硬件协同设计中的关键技术之一,如何兼顾系统的性能和成本,达到两者的最佳结合,是软硬件划分的主要问题.针对单CPU多ASICs类型的目标结构,选取了遗传算法、禁忌搜索算法和模拟退火算法等全局优化算法进行系统的软硬件划分,并对3种算法的有效性进行了比较分析.     

Efficient heuristic and tabu search for hardware/software partitioning

Hardware/software (HW/SW) partitioning is a crucial step in HW/SW codesign that determines which components of the system are implemented on hardware and which ones on software. It has been proved that the HW/SW partitioning problem is NP-hard. In this paper, we present two approaches for HW/SW partitioning that aims to minimize the hardware cost while taking into account software and communication constraints. The first is a heuristic approach that treats the HW/SW partitioning problem as an extended 0–1 knapsack problem. In the second approach, tabu search is used to further improve the solution obtained from the proposed heuristic algorithm. Experimental results show that the proposed algorithms outperform a recently reported work by up to 28 %.     

基于UML的软硬件协同设计方法

嵌入式系统软硬件协同设计中关键步骤之一是软硬件划分。文中通过介绍现有嵌入式系统的协同设计方法,如:VULCAN,COSYMA和POLIS,指出了现有方法的缺点,提出了一种改进的基于UML的新方法。使用UML建立系统模型,根据UML的图例,采用二叉树的结构,计算出每个步骤的成本;采用改进的遗传算法,加快收敛的速度,提高解的质量。在算法库和成本库中对系统的软硬件进行划分,通过协同综合,达到协同仿真和验证的目的。     

Codesign from cospecification

Describes an object-oriented codesign specification approach designed to eliminate the bias introduced from using more commonplace software or hardware specification languages. The goal is to investigate automated partitioning of behavior into hardware and software. The design methodology allows gradual, continuous repartitioning of codesign operations during design. For instance, designers might start with an all-software implementation and check the implementation's functionality: they might then refine the implementation over time to a mixed hardware-software implementation. At the system level, the authors use an object-oriented approach to identify the basic objects and associated functions of a system. They divide them into three groups: hardware, software, and codesign . They represent the codesign group's objects and functions using a prototype codesign specification language, Object-Oriented Functional Specifications (OOFS), which lets one describe system state in objects and write object methods as pure functions. Thus, the authors can describe complex systems without biasing the implementation toward hardware or software     

A framework for hardware/software codesign

It is argued that a hardware/software codesign methodology should support the following capabilities: integration of the hardware and software design processes; exploration of hardware/software tradeoffs and evaluation of hardware/software alternatives; and model continuity. A codesign methodology that supports many of these capabilities is outlined. The methodology is iterative in nature and serves to guide codesign exploration with the uninterpreted/interpreted modeling approach. It integrates performance (uninterpreted) models and functional (interpreted) models in a common simulation environment     

A Codesign Approach to Real-time High Precision Control

A new approach to design a high precision real-time control system for a spring forming machine is presented. This system is designed to satisfy the required high motor speed command signal and the product to product tolerance is limited to 0.1%. An innovative variable pulse generation algorithm is proposed for the activation of the motor in order to meet the stringent specifications. Because of the high speed command, software implementation of this algorithm would not be viable as this is intended to be a low cost automation system.To further enhance the system performance, an overall system architecture to incorporate a hardware solution is proposed. This new architecture comprises hardware and software functionality such that the codesign methodology is employed for the partitioning of the design procedures. Within this architecture, software development includes a user-friendly, safety and fault detection facility to improve the human-machine interface. This new precision control system meets the required performance specifications with only two-pieces of 2K gates Field Programmable Gate Array (FPGA) Actel chips are required for the implementation.     

A model and methodology for hardware-software codesign

A behavioral model of a class of mixed hardware-software systems is presented. A codesign methodology for such systems is defined. The methodology includes hardware-software partitioning, behavioral synthesis, software compilation, and demonstration on a testbed consisting of a commercial central processing unit (CPU), field-programmable gate arrays, and programmable interconnections. Design examples that illustrate how certain characteristics of system behavior and constraints suggest hardware or software implementation are presented     

嵌入式系统软硬件划分方法探索

提出了克隆选择算法在软硬件划分中的应用,讨论了目标函数、系统约束、抗体编码、克隆选择和变异等问题的处理。实验结果表明该算法具有较快的收敛速度,并获得了近似最优解。     

基于遗传算法的可重构系统软硬件划分

在考虑动态部分重构及重构延时等特征的基础上,采用遗传算法及其与爬山算法的融合实现可重构系统软硬件任务的划分,并采用动态优先级调度算法进行划分结果的评价。实验表明,在可重构系统的资源约束等条件下,算法能够有效地实现应用任务图到可重构系统的时空映射。     

可重构系统中软硬任务划分方法研究

软硬件任务划分是可重构系统开发过程中的重要设计步骤,其划分结果直接影响到可重构系统的性能。目前的软硬件任务划分技术大多只考虑了对应用程序或算法的划分结果,忽略了FPGA在配置和通信时的开销,从而导致实际应用效果不理想。介绍了一种基于性能评估的软硬件任务划分方法,即通过对FPGA计算开销、配置开销、通信开销的预评估测试,结合改进的模拟退火算法得出可重构系统中的软硬任务划分结果。实验结果表明,该划分方法具有较好的划分效果和算法收敛速度。     

嵌入式系统的软硬件划分

嵌入式系统软硬件协同设计中的关键步骤之一是软硬件划分。现有的许多软硬件划分方法都试图捕获太多有关划分问题和目标结构的细节，可扩展性差。本文提出了一种简化的软硬件划分问题模型，这种简化模型能分别对不同的划分问题进行形式化定义。在此模型的基础上，本文给出了基于ILP的算法和遗传算法。实验结果表明，我们的遗传算法能有效地解决千万个节点规模的划分问题，并获得近似最优解。     

嵌入式系统软硬件自动划分方法研究

软硬件划分一直是嵌入式系统软硬件协同设计中的难点,如果离开具体系统,单纯的软硬件划分,其性能很难评估。本文提出基于系统体系结构,应用遗传算法来进行多目标优化的软硬件自动划分方法。在具体设计中,使用数据流图对系统建模,采用邻接表进行个体编码,定义交叉、变异操作,同时引入小生境技术,保持解的多样性。该方法为嵌入式系统软硬件自动划分提供一种新思路。     

通过遗传算法进行系统级软硬件划分

介绍采用遗传算法解决软硬件划分问题，具体讨论在遗传算法实现过程中的编码和解码，适应值函数的选取，选择，交叉，变异算子的实现、收敛准则的决定等问题的处理，与已发表文献的处理方法进行比较，最后通过随机实验取得好的结果。     

约束驱动与松弛时间消除相结合的硬/软件划分算法

硬/软件划分是硬/软件协同设计的关键问题之一．在分析了已经被提出的硬/软件划分算法中存在的问题之后，提出了一种基于约束驱动和松弛时间消除相结合的硬/软件划分算法．首先是获取结点面积—时间(A—T)曲线的方法，然后比较时间约束紧迫度与阈值的大小，决定结点是用硬件还是软件执行．硬/软件面积的约束紧迫度决定硬/软件执行面积，通过A—T曲线找出对应的执行时间．最后，消除结点之间存在的松弛时间进一步优化设计．     

多选择软硬件划分问题的计算模型与动态规划算法

软硬件划分是软硬件协同设计的关键环节,划分的结果直接影响目标系统的设计质量。因此,对于一个给定的应用程序,为了使得目标系统快速执行且成本低廉,合理的划分策略十分重要。由于单个任务具有多种不同的硬件实现方式,与传统的单一硬件实现方式的软硬件划分问题相比,多选择的软硬件划分更能客观地反映现实应用。这导致问题的求解更具挑战性,它们已被证明是NP完全问题。基于多核处理器片上系统并针对任务图为二叉树的应用,建立了多选择软硬件划分问题的计算模型,并提出了解决该问题的动态规划算法。实验结果表明,当问题规模适中时,所提动态规划算法能够有效地获得精确解,并展示了算法的计算能力与硬件面积限制之间的关系。     

What's in a name [embedded systems]

Hardware/software codesign grew out of system-level synthesis. ASICs offer performance advantages at the expense of post-design- time programmability. This contrasts with computer architecture, which focuses on support for a wide variety of end-use programming scenarios. Currently neither hardware synthesis nor hardware/software codesign describes the system-level design represented in CODES+ISSS. CODES were the name of the International Conference on Hardware/Software Codesign. ISSS was the name of the International Symposium on System Synthesis.     

A two-level cosimulation environment

Hardware/software codesign seeks to integrate system level, hardware, and software design. Ideally, we would like tools that allow rapid evaluation of design decisions and a full exploration of the design space. Available tools are often too slow and concentrate on the low level cosimulation of hardware and software parts, after the design has been partitioned. We are attempting to remedy these problems with Tosca (Tools for System Codesign Automation), a hardware/software codesign environment. Targeted at single chip implementations consisting of a CPU core cell and dedicated hardware, Tosca performs a high level cosimulation for what-if analyses before hardware/software cosynthesis. After cosynthesis, Tosca generates simulatable software to be run on a retargetable instruction level model of the CPU. The software and hardware bound parts are then cosimulated using a commercial VHDL simulator. The performance of the low level cosimulation strategy and the high level simulator is remarkable. Low level cosimulation performance is about that of dedicated CPU software emulators-7200 pseudo assembly instructions per second. High level cosimulation is three times faster than the low level cosimulation. Both simulators allow functional debugging by interfacing to a commercial waveform visualizer (Mentor Graphics SimView). Engineers have used Tosca to redesign a commercial link controller     

基于免疫原理的逻辑电路设计算法

硬件进化是基于进化计算和可重构硬件的新兴研究领域。逻辑电路的进化设计是硬件进化的主要研究方向之一。文章将生物免疫系统的进化非选择机制引入到逻辑电路设计中,提出了相应的逻辑电路设计算法,并给出了该文算法和进化算法的对比实验结果,结果表明该文算法更加有效。