An Integrated Approach to the Design of Processor Arrays with Systolic Organization of Computations

An integrated approach is proposed to the design of economically efficient and high-performance processor arrays with systolic organization of computations. The approach includes the construction of VLSI-oriented versions of locally recursive algorithms and synthesis of new architectures of processor arrays for transforming algorithms that maximally take into account fundamental restrictions of VLSI technology. Within the framework of this approach, strategies are developed for obtaining the above-mentioned algorithms and architectures.     

低功耗并行的二维离散小波变换的VLSI结构

提出了一种基于提升算法的低功耗并行的二维离散小波变换的VLSI结构。提出结构的同时进行行和列方向的处理,不需要额外的缓存来存储用于列变换的中间变换系数。通过分时复用关键的运算功能模块,该结构同时可以对两行数据进行处理,硬件的利用率达到100%。边界对称扩展通过嵌入式电路实现,大大降低了需要的片上存储器的数量以及对片外存储器的访问,有效地降低了系统的功耗。     

Fifth generation and VLSI architectures

Most Western Governments (USA, Japan, EEC, etc.) have now launched national programmes to develop computer systems for use in the 1990s. These so-called Fifth Generation computers are viewed as “knowledge” processing systems which support the symbolic computation underlying Artificial Intelligence applications. The major driving force in Fifth Generation computer design is to efficiently support very high level programming languages (i.e. VHLL architecture).

Historycally, however, commercial VHLL architectures have been largely unsuccesful. The driving force in computer designs has principally been advances in hardware which at the present time means architectures to exploit very large scale integration (i.e. VLSI architecture).

This paper examines VHLL architectures and VLSI architectures and their probable influences on Fifth Generation computers. Interestingly the major problem for both architecture classes is parallelism; how to orchestrate a single parallel computation so that it can be distributed across an ensemble of processors.     

European trends in library development

The time-to-market and cost constraints of designing VLSI circuits, together with increasing complexity, necessitate a structured design methodology. Such a methodology should be based on an extensive use of libraries of generic components and previously designed macro blocks. An ideal library for modern design strategies that are based on a top-down structured approach is described. The concepts of portability, migratability, and interoperability of libraries are discussed. It is shown that libraries capitalize on knowledge gained over generations of designs, and successful libraries demand a serious effort at standardization     

FP──VLSI自动综合系统

ＦＰ—ＶＬＳＩ自动综合系统是一个集成化的ＶＬＳＩ自动设计工具，它能完成从并行算法到脉动算法到脉动结构再到逻辑结构最后到ＣＭＯＳ版图的自动综合过程．ＦＰ—ＶＬＳＩ系统以脉动阵列为ＶＬＳＩ的体系结构，采用具有良好代数性质的ＦＰ／Ｂ语言作为各层次的描述语言，通过程序变换进行综合和优化．该系统支持形式化的ＶＬＳＩ设计方法，能保证设计结果的正确性．     

Scalable communication architectures for massively parallel hardware multi-processors

Modern complex embedded applications in multiple application fields impose stringent and continuously increasing functional and parametric demands. To adequately serve these applications, massively parallel multi-processor systems on a single chip (MPSoCs) are required. This paper is devoted to the design of scalable communication architectures of massively parallel hardware multi-processors for highly-demanding applications. We demonstrated that in the massively parallel hardware multi-processors the communication network influence on both the throughput and circuit area dominates the processors influence, while the traditionally used flat communication architectures do not scale well with the increase of parallelism. Therefore, we propose to design highly optimized application-specific partitioned hierarchical organizations of the communication architectures through exploiting the regularity and hierarchy of the actual information flows of a given application. We developed related communication architecture synthesis strategies and incorporated them into our quality-driven model-based multi-processor design methodology and related automated architecture exploration framework. Using this framework we performed a large series of architecture synthesis experiments. Some of the results of the experiments are presented in this paper. They demonstrate many features of the synthesized communication architectures and show that our method and related framework are able to efficiently synthesize well scalable communication architectures even for the high-end massively parallel multi-processors that have to satisfy extremely stringent computation demands.     

有效的JPEG2000小波变换VLSI结构设计

基于提升的小波变换算法,提出了一种有效的JPEG2000小波变换的VLSI实现结构。采用了时分复用技术优化结构设计,实现了数据变换的细节分量和近似分量交替输出,以及有效减少了所用乘法器、加法器运算单元和寄存器单元数量,从而有效减少系统占用面积和功耗。该结构实现简单、规则,具有很好的扩展性,非常适合于VLSI设计实现。     

MDE for SoC design

We employ the principles of model-driven engineering to assist the design of system-on-chip (SoC) architectures. As a concrete example, we look at the MICAS architecture, for which we propose a graphical specification language, defined via metamodeling techniques, that models the architecture at different abstraction levels. Model transformations are defined to support the refinement of MICAS specification towards implementation. In addition, several libraries are put in place, to enable reuse and automation throughout the design process. Tool support for editing the specifications, enforcing their consistency, and for running the transformations is provided via the Coral modeling framework. The approach shows that model-driven engineering can be seen as an enabler in providing computer-aided software engineering (CASE) tool support and automation for the development of SoC architectures.     

H.264/AVC中CAVLC解码器的硬件设计与实现

设计了一种基于H.264标准的CAVLC解码器,码流输入单元采用桶形移位器,以实现单周期解一个句法元素,在各解码模块中采用码表分割、算术逻辑替代查表、零码字跳转等关键技术,在减少路径延迟和提高系统吞吐率的同时,节省了硬件开销。整个设计采用Verilog语言实现,在XILINX的ISE8.2开发环境下通过FPGA验证,使用Design Compiler在SMIC0.18μm CMOS单元库下综合,时钟最高频率可以达到165MHz。本设计可满足实时解码H.264高清视频的要求。     

Internal architecture design and freeform fabrication of tissue replacement structures

Modeling, design and fabrication of tissue scaffolds with intricate architecture, porosity and pore size for desired tissue properties presents a challenge in tissue engineering. This paper will present the details of our development in the design and fabrication of the interior architecture of scaffolds using a novel design approach. The interior architecture design (IAD) approach seeks to generate layered scaffold freeform fabrication tool path without forming complicated 3D CAD scaffold models. This involves: applying the principle of layered manufacturing to determine the scaffold individual layered process planes and layered contours; defining the 2D characteristic patterns of the scaffold building blocks (unit cells) to form the Interior Scaffold Pattern; and the generating the process tool path for freeform fabrication of these scaffolds with the specified interior architecture. Feasibility studies applying the IAD algorithm to example models with multi-interior architecture and the generation of fabrication planning instructions will also be presented.     

Guarded attribute grammars

Contrary to a widely-held belief, it is possible to construct executable specifications of language processors that use a top-down parsing strategy and which have structures that directly reflect the structure of grammars containing left-recursive productions. A novel technique has been discovered by which the non-termination that would otherwise occur is avoided by ‘guarding’ top-down left-recursive language processors by non-left-recursive recognizers. The use of a top-down parsing strategy increases modularity and the use of left-recursive productions facilitates specification of semantic equations. A combination of the two is of significant practical value because it results in modular and expressively clear executable specifications of language processors. The new approach has been tested in an attribute grammar programming environment that has been used in a number of projects including the development of natural language interfaces, SQL processors and circuit design transformers within a VLSI design package.     

On the issue of application of cellular automata and neural networks methods in VLSI design

Comparative analysis of applications of two conceptually similar methods used for VLSI design is performed. The models are the cellular automata and the neural networks Specific features of each method are particularized. For the first time the end-to-end strategy of application of the cellular automata for the whole design flow correlating with block-hierarchical approach is proposed.     

VLSI Implementation of Discrete Wavelet Transform for Lossless Compression of Medical Images

This paper presents a VLSI architecture to implement the forward and inverse two dimensional Discrete Wavelet Transform (DWT), to compress medical images for storage and retrieval. Lossless compression is usually required in the medical image field. The word length required for lossless compression makes too expensive the area cost of the architectures that appear in the literature. Thus, there is a clear need for designing a cost-effective architecture to implement the lossless compression of medical images using DWT. The data path word length has been selected to ensure the lossless accuracy criteria leading a high speed implementation with small chip area. The pyramid algorithm is reorganized and the algorithm locality is improved in order to obtain an efficient hardware implementation. The result is a pipelined architecture that supports single chip implementation in VLSI technology. The implementation employs only one multiplier and 352 memory elements to compute all scales what results in a considerable smaller chip area (45 mm²) than former implementations. The hardware design has been captured by means of the VHDL language and simulated on data taken from random images. Implemented in a 0.7 μm technology, it can compute both the forward and inverse DWT at a rate of 3.5 512×512 12 bit images/s corresponding to a clock speed of 33 MHz. This chip is the core of a PCI board that will speedup the DWT computation on desktop computers.     

Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP)

As the growth of system complexity rapidly increases, the gap between Electronic System Level (ESL) and the Register Transfer Level (RTL) must be filled. Currently, Very Large Scale Integration (VLSI) and System-on-Chip (SoC) designs are multi-objective in nature, requiring simultaneous fulfillment of multiple parameters. Extensive research on Design Space Exploration (DSE) problems and synthesis of an application specific processor (ASP) design have been done until now but none of the prior works have focused explicitly on integrating a fast multi-objective architecture exploration mechanism with the architectural synthesis stages to formalize the design methodology of an application specific processor in case of multiple objectives. This paper proposes a design methodology of a multi-objective application specific processor by integrating an efficient multi-objective (area occupied, execution time and power consumption) exploration approach with the architecture synthesis process, useful for portable devices and many high end applications. The formalized steps of the design methodology for the ASP guarantees the designer an error free approach to design the system with strict limitations on compound operational constraints. The results of implementation of the designed ASP using the proposed design methodology in FPGA and ASIC have also been shown.     

Controlling software architecture erosion: A survey

Software architectures capture the most significant properties and design constraints of software systems. Thus, modifications to a system that violate its architectural principles can degrade system performance and shorten its useful lifetime. As the potential frequency and scale of software adaptations increase to meet rapidly changing requirements and business conditions, controlling such architecture erosion becomes an important concern for software architects and developers. This paper presents a survey of techniques and technologies that have been proposed over the years either to prevent architecture erosion or to detect and restore architectures that have been eroded. These approaches, which include tools, techniques and processes, are primarily classified into three generic categories that attempt to minimise, prevent and repair architecture erosion. Within these broad categories, each approach is further broken down reflecting the high-level strategies adopted to tackle erosion. These are: process-oriented architecture conformance, architecture evolution management, architecture design enforcement, architecture to implementation linkage, self-adaptation and architecture restoration techniques consisting of recovery, discovery and reconciliation. Some of these strategies contain sub-categories under which survey results are presented.We discuss the merits and weaknesses of each strategy and argue that no single strategy can address the problem of erosion. Further, we explore the possibility of combining strategies and present a case for further work in developing a holistic framework for controlling architecture erosion.     

A design methodology for synthesizing parallel algorithms and architectures

In this paper, a design methodology for synthesizing efficient parallel algorithms and VLSI architectures is presented. A design process starts with a problem definition specified in the parallel programming language Crystal and is followed by a series of program transformations in Crystal, each aiming at optimizing the target design for a specific purpose. To illustrate the design methodology, a set of design methods for deriving systolic algorithms and architectures is given and the use of these methods in the design of a dynamic programming solver is described. The design methodology, together with this particular set of design methods, can be viewed as a general theory of systolic designs (or multidimensional pipelines). The fact that Crystal is a general purpose language for parallel programming allows new design methods and synthesis techniques, properties and theorems about problems in specific application domains, and new insights into any given problem to be integrated readily within the existing design framework.     

Optimal experiment design based on local model networks and multilayer perceptron networks

This paper addresses the topic of model based design of experiments for the identification of nonlinear dynamic systems. Data driven modeling decisively depends on informative input and output data obtained from experiments. Design of experiments is targeted to generate informative data and to reduce the experimentation effort as much as possible. Furthermore, design of experiments has to comply with constraints on the system inputs and the system output, in order to prevent damage to the real system and to provide stable operational conditions during the experiment. For that purpose a model based approach is chosen for the optimization of excitation signals in this paper. Two different modeling architectures, namely multilayer perceptron networks and local model networks are chosen and the experiment design is based on the optimization of the Fisher information matrix of the associated model architecture. The paper presents and discusses feasible problem formulations and solution approaches for the constrained dynamic design of experiments. In this context the effects of the Fisher information matrix in the static and the dynamic configurations are discussed. The effectiveness of the proposed method is demonstrated on a complex nonlinear dynamic engine simulation model and an analysis as well as a comparison of the presented model architectures for model based experiment design is given.     

Matisse: an architectural design tool for commodity ICs

To accelerate industrial adoption of behavioral synthesis, we have developed Matisse, an architectural design tool that increases productivity without sacrificing area, performance, or power. Matisse's main difference from traditional behavioral synthesis tools is that it lets the designer play a key role. It allows the designer to make major decisions about styles, protocols, parallelism, delays, and partial or even complete architectures before the behavioral synthesis phase starts. Then it enables the designer to incorporate these decisions into the architecture using behavioral synthesis. Matisse supports the diverse design practices required for commodity IC design by giving the designer fine-grain control of behavioral synthesis tasks