一款RFID低噪声放大器的设计与仿真

电子标签的广泛应用对UHF RFID(超高频射频识别)阅读器的性能提出了更高的要求.低噪声放大器能降低系统的噪声和提高接收机灵敏度,是接收系统的关键部件.设计的LNA应用于UHF RFID阅读器前端,要求工作频率为900一930MHz,噪声系数小于1dB,带内增益大于15dB以及高线性度指标包括输出1dB压缩点大于15dBm和输出三阶互调点大于30dBm.结合相关设计理论,利用安捷伦科技的E-PHEMT(增强型伪高电子迁移率晶体管)ATF54143,完成了电路设计并通过ADS2006对直流偏置、输入输出匹配以及源极加负反馈进行优化等仿真,结果表明:电路的噪声系数可达到0.54dB,功率增益高达23.4dB,输入、输出匹配良好,各种线性度指标也完全符合设计要求.     

高效率线性功率放大器设计

3G信号的高峰均比和快速的包络变化为基站功率放大器的设计提出了新的挑战。结合Doherty技术与基带多项式预失真技术,设计了一款高效率线性功率放大器。仿真分析得到,放大器在输出为P1dB到回退6dB的范围内,效率超过38.4%。使用码率为3.6864Mcps的CDMA2000信号源测试,在输入功率为38.5dBm时,其输出信号的ACPR达到-45dBc。本设计在线性放大的条件下实现了从P1dB处回退6dB范围的高效率放大器。     

S波段E类功率放大器的设计

开关模式E类功率放大器的理论效率可达100%,可用于天气雷达发射机系统中。采用GaN HEMT器件,设计了一个在2.8 GHz频点下的E类功率放大器,输出功率达到40 dBm,PAE为67%,增益为13 dB。此外,设计的微带负载网络对谐波进行了有效抑制。     

平衡功率放大器的设计与实现

设计了一个工作频段为902MHz～928MHz、输出功率为32dBm、应用于读卡器系统的末级功率放大器。为了在工作频段内实现平坦的功率增益并获得良好的输入、输出驻波比,本功率放大器采用平衡放大技术设计。仿真优化和实际测试表明,在整个工作频段内放大器的增益平坦度小于±0.5dB,输入、输出驻波比小于1.5,完全满足设计指标要求。     

驱动级功率放大器的设计与实现

设计了一个工作频段在902 MHz～928 MHz,输出功率为19 dBm、功率增益高达27 dBm、应用于射频识别(RFID)系统的驱动级功率放大器。为缩短功率放大器的研发周期并提高其开发的成功率,设计运用了仿真优化和实际测试相结合的方法。测试结果与仿真结果的高度一致性验证了这种方法的有效性。     

E类射频功率放大器设计

基于0.18μm CMOS工艺,采用包含增益驱动级在内的两级电路结构,设计了一个工作频率为2.4GHz的E类开关模式功率放大器,并实现了全片集成.电路通过负载牵引技术获得最佳输出负载,在2V电源电压下经ADS2005A仿真,当输入信号功率为-10dBm时,获得约21.5dBm的输出功率,功率增益为31dB,功率附加效率达到57.69%的较好结果.     

带自适应控制的直放站线性功率放大器

线性功率放大器是CDMA直放站的核心模块.本文设计的带自适应控制的线性功放,其功率增益G为48 0.8dB,1db压缩点输出功率≥37dBm,带内渡动≤0.8dB,互调失真IMD3≤-15dBm,IMD5≤-25dBm,输入输出端口驻波比VSWR≤1.3,增益步进衰减ATT范围为31dB,自动电平控制ALC范围为20dB,符合直放站的应用要求.     

2.4GHz0.18um CMOS功率放大器设计

文章介绍了采用TSMC 0.18um CMOS工艺设计的2.4GHz WLAN(无线局域网)功率放大器,放大器采用并联拓扑结构设计,改善了功率附加效率(PAE).在3.3V工作电压下,其压缩点输出功率为21dBm,最大输出功率22.3dBm,最大功率附加效率PAE高于38％,可应用于无线局域网802.11b标准的系统.     

基于谐波抑制的小型化高效率功率放大器设计

针对传统VHF波段功率放大器存在的体积大、效率低、谐波干扰严重等问题,利用集总参数元件设计了一款工作于该波段的小型化、高功率、高效率功率放大器。通过在功率放大器的输出匹配电路中引入多级LC谐振网络,实现了对谐波分量的有效抑制,提高了功率放大器的线性度和效率,也改善了电磁兼容性。实物测试结果表明,该功率放大器的饱和输出功率约为44.9 dBm,饱和功率增益为14 dB,功率附加效率为62%,性能优良,具有较好的实际工程应用价值,可广泛应用于航空、航天等领域。     

一种带有巴伦电路的24 GHz上混频器设计

设计了一个24 GHz上变频混频器,基于吉尔伯特结构全集成了3个片上巴伦电路。采用gm/I方法协调晶体管大小为了获得较好的转换增益、隔离度与电路耗散功率。电路实现采用厦门三安0.5μm PHEMT工艺,5 V电压供电,在本振LO为0 dBm时,转换增益为9 dBm。工作在24 GHz频段时,1 dB压缩点为-20 dBm,混频器的最大输出功率为-10 dBm,射频输出端口与本振的隔离度大于32 dB,整个电路直流功耗40 mW,芯片面积为1 mm×1.3 mm。     

Performance comparison of a single and multiband power amplifiers using IHP 0.25 μm SIGe HBT technology

In this work, a single‐band power amplifier (PA) with a fixed‐frequency/band output matching network and multiband PA with a switch‐tuned output matching network is designed, using IHP (Innovations for High Performance), 0.25 μm‐SiGe HBT process. The behavior of the amplifiers has been optimized for 2.4 GHz (WLAN), 3.6 GHz (UWB‐WiMAX), and 5.4 GHz (WLAN) frequency bands for a higher 1‐dB compression point and efficiency. Multiband characteristics of the amplifier were obtained by using a MOS‐based switching network. Two MOS switches were used for tuning the band of the output matching network. Postlayout simulations of the multiband‐PA provided the following performance parameters: 1‐dB compression point of 25.2 dBm, gain value of 36 dB, efficiency value of 12.8% operation and maximum output power of 26.8 dBm for the 2.4 GHz WLAN band, 1‐dB compression point of 25.5 dBm, gain value of 32 dB, efficiency value of 13.3% and maximum output power of 26.6 dBm for the 3.6 GHz UWB‐WiMAX band and 1‐dB compression point of 24.8 dBm, gain value of 23 dB, efficiency value of 12.5% and maximum output power of 26.3 dBm for the 5.4 GHz WLAN band. For the fixed‐band, at 3.6 GHz, the postlayout simulations resulted the following parameters: 1‐dB compression point of 25.5 dBm, gain value of 32 dB, efficiency value of 18% and maximum output power value of 26.8 dBm. Measurement results of the single‐band PA provided the following performance parameters: 1‐dB compression point of 20.5 dBm, gain value of 23 dB and efficiency value of 7% operation for the 2.4 GHz band; 1‐dB compression point of 25.5 dBm, gain value of 31.5 dB and efficiency value of 17.5% for the 3.6 GHz band; 1‐dB compression point of 22.4 dBm, gain value of 24.4 dB and efficiency value of 9.5% for the 5.4 GHz band. Measurement results show that using multistage topologies and implementing each parasitic as part of the matching network component has provided a wider‐band operation with higher output power levels, above 25 dBm, with SiGe:C process. These results proved that the PA, with switching/tunable output matching network, provides compatible performance parameters, when compared with the fixed‐band PA. The ability of being capable of operation in different frequency bands with compatible performance parameters, when compared with fixed‐band PA, multiband PA can be realized with additional less parasitics, area, and cost advantages. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

A class-E power amplifier with high efficiency and high power-gain for wireless sensor network

In the literature, a number of two-stage class-E power amplifiers have been reported for wireless sensor network (WSN) applications. However, they suffer from the requirement of larger silicon area, inductors with high quality factor, large number of off-chip decoupling capacitors, high input power, voltage stress handling capability and efficiency degradation due to finite on-resistance and surplus capacitance of switching transistors. In order to overcome these limitations and to enhance the power added efficiency, two novel two-stage class-E power amplifiers denoted as PA1 and PA2 are proposed in this paper. Both the amplifiers use a driver amplifier with capacitive feedback and pi-matching at the input. PA1 uses a main amplifier with negative-capacitance cascode topology. PA2 uses a diode connected NMOS auxiliary transistor with RC source degeneration in the driver amplifier, negative-capacitance cascode configuration with a parallel LC-tuning circuit in the main amplifier. To evaluate the efficacy of these circuits, the proposed power amplifiers are implemented in UMC 0.18-µm standard RFCMOS process with the supply voltage of 3.0 V and the operating frequency of 2.45 GHz and studied through post-layout simulation using Cadence Virtuoso (IC616) Analog Design Environment. From this study, it is found that the proposed power amplifiers have the power added efficiency of (45.02 %, 54.87 %), the saturated output power at 1-dB compression point (P1-dB) of (21.52 dBm, 23.17 dBm), the power gain of (27.29 dB, 28.74 dB) and the output referred intercept point (OIP3) of (19.41 dBm, 22.67 dBm), respectively. Both of these power amplifiers have higher figure of merit (FoM) of (53.80, 57.98) when compared to other reported works. It is observed that the proposed power amplifiers are suitable to operate under low input power of -8 dBm and hence it meets the requirement of WSN applications.

     

Analysis and improvement of PSRR in an envelope‐tracking power amplifier using a common‐drain amplifier topology

A common‐drain power amplifier (PA) for envelope tracking systems is presented. In envelope tracking, the main PA operates mostly in compression and the power supply rejection ratio (PSRR) is not high. Furthermore, the output noise of the supply modulator can be mixed with the RF signal and generates out‐of‐band emissions. In this article, instead of using a common‐source topology, the PSRR of the envelope tracking PA is inherently improved by utilizing a common‐drain topology. A comprehensive analysis shows that the common‐drain topology is less sensitive to the supply noise, as compared to the conventional common‐source topology. The proposed common‐drain PA is implemented using a discrete LDMOS PD20010‐E RF transistor. Measurement results show that the PSRR of the proposed common‐drain PA is improved by up to 7 dB as compared to that of the common‐source PA. For a two‐tone input with 10 MHz bandwidth at the center frequency of 700 MHz, the power added efficiency (PAE) and IM3 of the envelope tracking common‐drain PA are 20% and ? 28 dBc, respectively, at an average output power of 33.4 dBm. The amplifier also shows a 12.4 dB power gain. Moreover, by utilizing the envelope tracking, the PAE is improved by more than 5%.     

A millimeter‐wave CMOS power amplifier design using high‐Q slow‐wave transmission lines

A three‐stage 60‐GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High‐quality‐factor slow‐wave coplanar waveguides (S‐CPW) were used for input, output and inter‐stage matching networks to improve the performance. Being biased for Class‐A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3‐dB bandwidth of 8.5 GHz. The measured 1‐dB output compression point (OCP_1dB) and the maximum saturated output power P_sat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm² (875 × 600 μm²) including all the pads, whereas the effective area is only 0.24 mm². In addition, the performance improvement of the PA in terms of G, OCP_1dB, P_sat, PAE and the figure of merit using S‐CPW instead of thin film microstrip have been demonstrated. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:99–109, 2016.     

CMOS stacked folded differential structure power amplifier for high power RF application

This article describes the feasibility of a Power Amplifier (PA) in 0.13 μm CMOS technology from STMicroelectronics for high power applications. To obtain a high output power with a good linearity, a new topology called Stacked Folded Differential Structure (SFDS) is proposed. It allows obtaining similar power performances to a PA with DAT in a lower die area. This PA provides 23 dBm of maximum output power (P_max) with 20% of power added efficiency (PAE) at 1.95 GHz. The linear gain is equal to 11 dB and the output power at 1 dB compression point (OCP₁) achieves 21 dBm. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010.     

A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology

Sub-threshold leakage is a major issue for low power circuits design, especially for SRAM design in SoC. Sub-threshold leakage can be decreased by scaling down supply voltage. However, this may dramatically increase the circuit delay. In this paper, we propose a novel 6 T SRAM array structure with a switch module which operates in the near threshold region to reduce the leakage current. In order to verify our proposed leakage reduction scheme, we designed and simulated an 8192 kB SRAM array based on a 16 KB single port SRAM cell memory model in 55 nm process. Several 6 T SRAM Array instances are implemented in 55-nm 1P6M CMOS technology to measure the standby current of the proposed scheme as well. With the proposed technique~ we achieved 28.3% reduction for leakage current compared to traditional 6 T SRAM array, in standby mode where gate leakage is dominant. The total penalty is 2% area increase and 1% speed reduction.     

Investigation on harmonic spur characteristics of hybrid integrated LDMOS and AlGaN/GaN power amplifiers at different temperatures

The harmonic spur characteristics of a hybrid integrated S‐band power amplifier (PA), consisting of both stages of LDMOSFET and AlGaN/GaN HEMT, are studied at different temperatures. The PA offers a peak output power of 50 dBm (100 W) with power added efficiency higher than 50%, and adjacent channel power ratio performance is less than ?30 dBc. A temperature test chamber is employed for measuring the harmonic spur of PA from 233 to 393 K, and its linear response to temperature is captured at high output power level.