A novel hardware-oriented Kohonen SOM image compression algorithm and its FPGA implementation

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The major drawback of the software implementation of this technique is its very computational intensive task. Fortunately, the structure is fairly easy to convert into hardware processing units executing in parallel. The resulting hardware system, however, consumes much of a microchip’s internal resources, i.e. slice registers and look-up table units. This results in utilising more than a single microchip to realize the structure in pure hardware implementation. Previously proposed K-SOM realizations were mainly targetted on implementing on an application specific integrated circuit (ASIC) with low restriction on resource utilization. In this paper, we propose an alternative architecture of K-SOM suitable for moderate density FPGAs with acceptable image quality and frame rate. In addition, its hardware architecture and synthesis results are presented. The proposed K-SOM algorithm compromises between the image quality, the frame rate throughput, the FPGA’s resource utilization and, additionally, the topological relationship among neural cells within the network. The architecture has been proved to be successfully synthesized on a single moderate resource FPGA with acceptable image quality and frame rate.     

基于模糊自组织模式的智能控制加温系统

论文介绍一种新型的智能控制加温系统。该系统硬件上以MCS-51系列STC89C52芯片为核心,利用Pt100电阻结合桥式电路和仪用放大电路对温度进行高精度感知作为系统输入信息,加温电路为多分枝自组织电路;通过构建模糊自组织模式的控制算法,系统将温度感知信息经智能控制算法分析处理后,选择加温电路的构成方式,实现对物体加温精度和速度优化的智能控制。研制系统的实际测试结果表明,这样的系统可获得高的温度控制精度,也能优化加热速度。     

Analog implementation of pulse-coupled neural networks

This paper presents a compact architecture for analog CMOS hardware implementation of voltage-mode pulse-coupled neural networks (PCNN). The hardware implementation methods shows inherent fault tolerance specialties and high speed, which is usually more than an order of magnitude over the software counterpart. A computational style described in this article mimics a biological neural network using pulse-stream signaling and analog summation and multiplication, pulse-stream encoding technique uses pulse streams to carry information and control analog circuitry, while storing further analog information on the time axis. The main feature of the proposed neuron circuit is that the structure is compact, yet exhibiting all the basic properties of natural biological neurons. Functional and structural forms of neural and synaptic functions are presented along with simulation results. Finally, the proposed design is applied to image processing to demonstrate successful restoration of images and their features.     

WSN-UAV基于FPGA的异步带优先级数据转发轮询控制系统

在林、农作物监测作业中,可通过散布无线传感器节点形成的自组织WSN收集作物环境信息。将UAV应用于分簇式WSN作为移动的数据收集节点sink时,UAV不仅需要转发各簇首节点的信息,还需转发自带传感器检测到的重要信息。为了保证UAV传感器检测信息及时转发,并进一步降低簇首节点能耗,延长WSN网络寿命,提出异步带优先级的数据转发轮询控制系统方案,应用马尔可夫链和概率母函数进行建模以分析系统性能。用自带异步读写FIFO功能的FPGA作为主控器件,基于FPGA设计该轮询系统硬件电路结构,验证了该轮询控制系统的可行性和高效性。实验结果表明,该方案能保证UAV及时转发重要数据,缩短服务延迟,提高WSN能耗效率,优化系统性能。     

基于ADS1298的新型脑电信号采集前端设计

以ADS1298转换器为基础,通过将高精度模数转换与数字降噪处理技术结合来简化信号调理硬件电路设计,利用芯片内部集成的右腿驱动模块设计了右腿驱动信号电路,实现一种精度高、体积小、低功耗的多通道脑电信号采集前端,并讨论了实现更多通道脑电信号采集的多芯片级联技术,可广泛应用于便携式多通道脑电信号采集设备。     

Intrafield transform image coding of composite video

Two different schemes, i.e. adaptive and nonadaptive systems, are developed for intrafield transform (2d-DCT) image processing of a digital NTSC color composite video signal, sampled at three times the color subcarrier frequency. The fast transform algorithm for 2d-DCT (8 × 8 subblock) is used. Based on the statistics of the transform coefficients, variable word length quantizers, optimized for minimizing the mean square error, are developed. These techniques lead to reduced bit rates for transmitting color video at broadcast standards. The performance of adaptive system is much better than that of nonadaptive system. Although the necessary hardware will likely exceed what is needed for a nonadaptive system, the benefits will more than offset the hardware complexity. The effect of channel noise in the adaptive system is investigated in terms of severity and propagation patterns. This is carried out by using a forced error scheme which selectively forces the error to occur in the different types of coding bits. Error propagation patterns are studied by series of computer printouts.     

Research of Intelligent Circuit Breaker Controller Based on CAN Bus

I. INTRODUCTION The circuit breaker is an important device in electric power distributing and circuit protection, which can protect electric distributing system, electric load system and overload, short circuit, unidirectional earthing and under-voltage that happen to apparatus. So the circuit breaker can avoid or reduce loss of electric system and apparatus. The tradition low-voltage circuit breaker adopt electromagnetic and thermo-electrical release, which has some shortages such as lon…     

Time-to-Collision estimation from motion based on primate visual processing

A population coded algorithm, built on established models of motion processing in the primate visual system, computes the time-to-collision of a mobile robot to real-world environmental objects from video imagery. A set of four transformations starts with motion energy, a spatiotemporal frequency based computation of motion features. The following processing stages extract image velocity features similar to, but distinct from, optic flow; "translation" features, which account for velocity errors including those resulting from the aperture problem; and finally, estimate the time-to-collision. Biologically motivated population coding distinguishes this approach from previous methods based on optic flow. A comparison of the population coded approach with the popular optic flow algorithm of Lucas and Kanade against three types of approaching objects shows that the proposed method produces more robust time-to-collision information from a real world input stimulus in the presence of the aperture problem and other noise sources. The improved performance comes with increased computational cost, which would ideally be mitigated by special purpose hardware architectures.     

基于DSP的Fe83 Ga17合金磁致伸缩传感器信号处理系统设计

为了突破传统Fe-Ni磁致伸缩材料测量量程的限制,采用了一种新型的Fe83 Ga17材料。讨论了传统硬件比较电路方法,为了解决硬件比较电路存在的问题,设计了基于数字信号处理器（ DSP）的磁致伸缩位移传感器信号处理系统,包括A/D采样模块、FIR滤波模块和位移测量模块。考虑到环境因素带来的误差,进行温度补偿设计,修正了测量结果。实验结果显示：基于DSP的信号系统能够达到较高的测量精度,对磁致伸缩位移传感器的实际应用有积极的意义。     

Modeling selective attention using a neuromorphic analog VLSI device

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.     

软判决修正下的语音增强算法在数字信号处理器上的实现与优化

针对低信噪比情况下,传统谱估计语音增强算法性能下降的问题,提出了一种结合语音存在概率和人耳听觉掩蔽效应的软判决短时谱估计算法。该算法在低信噪比的情况下保护微弱的语音信号,减少语音谱的失真。同时介绍了基于TMS320C5502数字信号处理器的嵌入式系统,重点讨论了系统总体方案和主要功能模块的硬件设计,并且结合数字信号处理器的结构特点,给出了该算法系统平台移植和优化的方法。系统测试表明,硬件平台工作稳定可靠,针对硬件资源的移植和优化显著地提高了系统的处理速度,满足实时性的要求,且输出语音在去噪度与失真之间很好地平衡,优于传统的谱减算法。     

CMOS图像传感器的自适应降噪方法研究

提出了一种用于CMOS图像传感器的新型自适应降噪方法,并进行了逻辑电路实现。该方法通过运动检测和边缘检测技术进行噪声功率统计和分析,选择性的利用中值滤波、均值滤波以及运动自适应滤波方法,对传感器输出图像进行了数字降噪处理。实验表明本文方法降低了高斯噪声和椒盐噪声的影响,有效提高了图像质量和峰值信噪比。其结构易于电路实现,适用于CMOS图像传感器内部的实时降噪处理。     

基于TDC的微小电容测量电路的设计

提出一种基于TDC(时间数字转换)的微小电容测量电路的设计方案。该电路具有功耗低、体积小、抗干扰性强、分辨力高、刷新率高的特点。详细阐述了测量电路的基本原理、具体实现、参数配置、标定和抗干扰设计,并且通过测量0pF～3pF范围的固定电容和动态电容验证了电路的性能。试验表明电路在10Hz刷新频率下分辨力为6aF;电路在13kHz刷新频率下分辨力为610aF;ENOB(有效精度位)最高可达22位。     

A passive auto-focus camera control system

This paper presents a passive auto-focus camera control system which can easily achieve the function of auto-focus with no necessary of any active component (e.g., infrared or ultrasonic sensor) in comparison with the conventional active focus system. To implement the technique we developed, the hardware system including the adjustable lens with CMOS sensor and servo motor, an 8051 image capture micro-controller, a field programmable gate array (FPGA) sharpness measurement circuit, a pulse width modulation (PWM) controller, and a personal digital assistant (PDA) image displayer was constructed. The discrete wavelet transformation (DWT), the morphology edge enhancement sharpness measurement algorithms, and the self-organizing map (SOM) neural network were used in developing the control mechanism of the system. Compared with other passive auto-focus methods, the method we proposed has the advantages of lower computational complexity and easier hardware implementation.     

基于DSP的多通道音频信号处理平台的设计

介绍了一种基于DSP的多通道音频信号处理平台的基本电路,设计了DSP与音频编解码器TLV320AIC23B的硬件接口,实现了四通道音频信号输入和输出,同时具有高性能、低功耗和便携等特点。该平台已经应用于有源抗噪声耳罩项目中。     

HSP50216在中频采样数字接收机中的应用

主要介绍了可编程四中频下变频器HSP50216的硬件结构和特点,给出了此芯片在中频采样数字接收机中的具体使用方法。试验证明这种方法较之传统模拟的超外差接收机简化了硬件实现电路,提高了信噪比。     

基于FPGA多波束成像的声纳系统设计

给出了一种基于FPGA的多波束成像声纳整机的硬件电路设计方案,介绍了该方案中各分系统的具体电路实现,以Xilinx公司的FPGA芯片作为核心器件,根据干端PC下发的控制指令实现对180个基元的发射接收电路的控制,完成数字波束形成,并将波束数据通过千兆网上传至干端PC进行显示。系统电路设计简洁,具有较强的灵活性和扩展性。文中介绍了系统的硬件架构,论证了多波束成像声纳系统接收前端和数字信号处理模块的硬件设计方案。实际测试结果表明,系统能够清晰地对水底地形特征进行实时成像,具有15帧/s的刷新率。     

电量计费数字化系统设计与分析

为适应电力系统＂数字化电网＂发展的需要,本文对电能计量的脉冲法和积算法两种方式进行分析,提出了硬件基础为V/F转换器和高精度单片机处理器芯片的数字化电度表,此方案主要是将电力系统终端计费方式进行数字化改造,这套新型电量计费自动化系统,采用全数字化的信息处理方式,可以非常方便地接入未来的＂数字化电网＂。     

1-Wire温度传感器在火灾报警系统中应用

1-Wire总线技术具有节省I/O资源、结构简单、成本低廉,便于总线扩展和方便维护等特点。文章中介绍了1-Wire总线技术数字温度传感器的基本特性与功能块图,数字温度传感器ROM命令和功能命令。阐述了1-Wire总线技术数字温度传感器供电方式。利用1-Wire总线技术使用多个数字温度传感器,实时时钟电路,键盘显示电路,串行存储器电路,RS485通信电路以及看门狗电路等,组成了火灾报警系统硬件系统。绘制了温度采集与处理流程图。采用多个传感器测量不同房间内的温度,可以设置不同房间的报警上限值,可以实现多个房间对应温度的显示和报警。1-Wire总线技术数字温度传感器已经成功地应用于火灾报警系统中。