校准仪中精密合成电阻的设计

介绍了校准仪中精密合成电阻的设计。该设计利用精密运算放大器缓冲输入电压,并通过数/模转换器调整施加于标准电阻上电压与电流的比例,从而改变电阻值。通过内置的精密电阻测量电路测算出运放的失调电压,并用数/模转换器自动补偿失调电压,可取得高精度的可编程合成电阻,以满足校准仪中电阻输出的要求。     

一种阵列电阻传感器的电阻检测电路设计

柔性电阻阵列传感器在生物信息检测领域有着巨大的应用,但由于阵列电阻间串扰的存在,使得该类传感器检测精度大大降低,本文基于等电势屏蔽方法设计实现了一种针对于阵列电阻检测的高准确性可变精度的检测电路,并通过Multisim进行阵列电阻检测仿真,经过仿真验证该电路最高可实现1%精度的阵列电阻检测。     

某导弹绝缘电阻测试仪采样电路的设计

为了提高某绝缘电阻测试仪的测试精度,基于最小二乘法,提出一种绝缘电阻测试中电源内阻人误差的修正方法。设计了一种滤波电路,并对滤波电路进行了仿真分析,可知滤波电路有效的减小了工频杂波的影响;设计了一种隔离放大电路,提高r系统的安全性;实验表明,上述措施有效的提高了测试的精度。     

电阻电路中的故障分析方法

介绍了电阻电路中故障分析依据的原理、常见故障的检查方法,通过实例说明如何定位故障的位置和性质,并指出在分析电路故障时应注意的问题。本文对分析电阻电路中的故障有一定的帮助。     

基于MSP430的微电阻测试仪的设计

传统测量微电阻的方法操作繁琐,且引线电阻和触点电阻对测量结果影响较大.本文设计的基于交流恒流源激励的微电阻测试仪由交流激励源、数字移相电路、信号调理电路以及A/D转换与显示电路等四部分组成.微电阻由交流激励源注入交流信号后通过高阻低噪声运算放大器AD620提取响应信号,再经过锁相放大电路测得其真实的响应电压,锁定后的信号克服了内部噪声和外部电磁干扰的影响,能够实现对微小电阻的准确测量.通过对样机的测试和比对标称值,该测试仪工作稳定,具有较高的测量准确度,方便携带和使用.     

电阻应变式力传感器低频冲击频率测量电路设计

针对采用压电式力传感器、冲击力传感器测量冲击频率存在成本高、安装不便等问题,设计了一种电阻应变式力传感器低频冲击频率测量电路。该电路根据电阻应变式力传感器的工作原理,首先采用放大电路将传感器输出信号放大,然后运用电压比较电路产生方波信号,最后采用单稳态触发电路对方波信号整形,从而得到标准的方波信号。实际应用表明,该电路工作稳定,测量精度较高。     

多路电阻式温度传感器超温巡检电路应用中的问题和分析

某产品中的多路温度超温巡检电路采用了低成本的模数混合设计,其中模拟电路用于完成电阻式温度传感器电阻(温度)值的测量及判断,数字电路用于完成10路电阻式温度传感器的切换;该电路的巡检周期为2s(5%),报警的最小电阻值为1050Ω在最初的设计中由于考虑欠周,在长期使用中该电路出现了器件易损坏和误报警等问题;通过对原设计进行改进,提高了产品的稳定性和可靠性,并提出了该类电路设计时应该注意的事项.     

电阻“神爪”绝技

电阻是电路中最常见、最基本的元器件，设计调试和焊接大多是从电阻开始的。在制作电路时，快速准确地选取和使用电阻非常关键。最常用的是四环和五环的色环电阻，在一大堆花花绿绿五颜六色的电阻中挑选一个符合要求的电阻是非常麻烦和困难的事，稍不注意就会因此而使电路不成功或烧毁，也常常因此而浪费时间和精力，甚至使电路的制作调试失败中途...     

电阻信号,模拟信号的变换电路

A/D转换电路是数字仪表必不可少的组成部分,传感器的电阻信号准确地变换成数字仪表的模拟信号是保证数字仪表精确度的重要第一步。测温的热电阻、应变片的力传感器、可变精密电阻的远传压力表和多圈精密电位器的浮球液位计等都是电阻信号的传感器,其输出的电阻信号和被测参数(温度、压力、液位等)呈现线性关系或非线性关系,需通过不同的变换电路转换为数字仪表的模拟信号。 UQZ型浮球液位计、YTZ型远传压力表和G分度号铜热电阻等,输出的电阻信号和被测参数量程呈线性关系,可采用普通电桥和放大电路,见图1。     

基于运放技术的精密电阻测量电路设计

本设计运用二片运算放大器uA741和LF356,构建一款实用精密电阻测量电路。利用运算放大器的电压放大倍数与外接电阻的关系原理设计本款的测量电阻的电路。文章对电阻的原理进行分析,通过调试测试数据说明电路的可行可靠。同时也引出通过参数的改变可以得到不同量程的电阻测量。     

Differential coupling contributes to synchronization via a capacitor connection between chaotic circuits

Nonlinear oscillators and circuits can be coupled to reach synchronization and consensus. The occurrence of complete synchronization means that all oscillators can maintain the same amplitude and phase, and it is often detected between identical oscillators. However, phase synchronization means that the coupled oscillators just keep pace in oscillation even though the amplitude of each node could be different. For dimensionless dynamical systems and oscillators, the synchronization approach depends a great deal on the selection of coupling variable and type. For nonlinear circuits, a resistor is often used to bridge the connection between two or more circuits, so voltage coupling can be activated to generate feedback on the coupled circuits. In this paper, capacitor coupling is applied between two Pikovsk-Rabinovich (PR) circuits, and electric field coupling explains the potential mechanism for differential coupling. Then symmetric coupling and cross coupling are activated to detect synchronization stability, separately. It is found that resistor-based voltage coupling via a single variable can stabilize the synchronization, and the energy flow of the controller is decreased when synchronization is realized. Furthermore, by applying appropriate intensity for the coupling capacitor, synchronization is also reached and the energy flow across the coupling capacitor is helpful in regulating the dynamical behaviors of coupled circuits, which are supported by a continuous energy exchange between capacitors and the inductor. It is also confirmed that the realization of synchronization is dependent on the selection of a coupling channel. The approach and stability of complete synchronization depend on symmetric coupling, which is activated between the same variables. Cross coupling between different variables just triggers phase synchronization. The capacitor coupling can avoid energy consumption for the case with resistor coupling, and it can also enhance the energy exchange between two coupled circuits.

     

基于低阈值单元的高性能低功耗设计方法

在高性能IC设计中对高低两种阈值电压技术进行比较,利用低阈值电压降低动态功耗的手段实现降低总功耗的目标,并分析出了两种阈值电压低功耗设计各自适应的电路类型。首先对40nm工艺中标准单元的内部功耗、时序、尺寸进行分析。接着在相同延时下对高阈值和低阈值两种标准单元所设计的反相器链时序电路的功耗进行对比分析。最后基于Benchmark和AES两种类型电路,分别采用高阈值和低阈值进行综合,对比得出在相同时钟周期下更低功耗的设计所对应的阈值电压设计方式。结果显示,在相同的时钟频率下,对动态功耗占据总功耗比例极大的电路使用低阈值设计得到的功耗更低。同样,在动态功耗比例不是极大的电路中,当低阈值综合的slack为正时,以及当高阈值综合的slack为负、低阈值的slack为0时,用低阈值设计功耗更低;而当高阈值、低阈值综合的slack都为0时,用高阈值设计功耗更低。     

运算放大器锁零电路分析及其改进

分别介绍了目前常用的由NPN型BJT和由N沟道JFET构成的运算放大器锁零电路的工作原理;针对N沟道JFET运算放大器锁零电路的弊端提出了相应的改进方法,即将控制回路中的二极管改为电阻以方便维修,将N沟道JFET改为P沟道JFET以简化计算机锁零控制电路;最后指出采用继电器进行运算放大器锁零可以消除残余电压。     

A Large Dynamic Range Floating Memristor Emulator With Equal Port Current Restriction

In this paper, a large dynamic range floating memristor emulator(LDRFME) with equal port current restriction is proposed to be achieved by a large dynamic range floating voltage-controlled linear resistor(VCLR). Since real memristors have not been largely commercialized until now, the application of a LDRFME to memristive systems is reasonable. Motivated by this need, this paper proposes an achievement of a LDRFME based on a feasible transistor model. A first circuit extends the voltage range of the triode region of an ordinary junction field effect transistor(JFET). The idea is to use this JFET transistor as a tunable linear resistor. A second memristive non-linear circuit is used to drive the resistance of the first JFET transistor. Then those two circuits are connected together and, under certain conditions, the obtained "resistor" presents a hysteretic behavior,which is considered as a memristive effect. The electrical characteristics of a LDRFME are validated by software simulation and real measurement, respectively.     

Depth-optimized reversible circuit synthesis

In this paper, simultaneous reduction of circuit depth and synthesis cost of reversible circuits in quantum technologies with limited interaction is addressed. We developed a cycle-based synthesis algorithm which uses negative controls and limited distance between gate lines. To improve circuit depth, a new parallel structure is introduced in which before synthesis a set of disjoint cycles are extracted from the input specification and distributed into some subsets. The cycles of each subset are synthesized independently on different sets of ancillae. Accordingly, each disjoint set can be synthesized by different synthesis methods. Our analysis shows that the best worst-case synthesis cost of reversible circuits in the linear nearest neighbor architecture is improved by the proposed approach. Our experimental results reveal the effectiveness of the proposed approach to reduce cost and circuit depth for several benchmarks.     

Automated passive filter synthesis using a novel tree representation and genetic programming

This paper proposes a novel tree representation which is suitable for the analysis of RLC (i.e., resistor, inductor, and capacitor) circuits. Genetic programming (GP) based on the tree representation is applied to passive filter synthesis problems. The GP is optimized and then incorporated into an algorithm which can automatically find parsimonious solutions without predetermining the number of the required circuit components. The experimental results show the proposed method is efficient in three aspects. First, the GP-evolved circuits are more parsimonious than those resulting from traditional design methods in many cases. Second, the proposed method is faster than previous work and can effectively generate parsimonious filters of very high order where conventional methods fail. Third, when the component values are restricted to a set of preferred values, the GP method can generate compliant solutions by means of novel circuit topology.     

Controllable decoding for automated analog circuit structure design

The decoding scheme is a major problem in automated analog circuit topology synthesis since decoding schemes bias synthesized circuit structures. However, the proper decoding scheme varies depending on the method to realize a given function. In this paper, a controllable decoding scheme is proposed in which the method to realize a function is controlled by a set of prototype circuits. Thus, the system can generate different types of analog circuits in a unified method. The prototype circuits are designed by a human and suggested to the system as hints of configurations of new analog circuits to be synthesized by the system. In the synthesis process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. A genetic algorithm is then used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are generated with a proposed technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through synthesis examples of a cubing circuit synthesis as a current-mode design and a logic circuit synthesis as a voltage-mode.The authors would like to thank the reviewers for their valuable comments. The authors would like to express special thank to Dr. Andrew M. Abo for English corrections.     

混沌态电阻测量电路的改进

提出了一种基于DSP的混沌态电阻测量新方法;用于电阻式传感器中微变电阻的测量,与已有的测量方案相比,具有更好的线性度和更小的误差,实测分辨力可达0.05Ω,它对测量电路参数要求不高,大幅度地降低了测量过程中的噪声;给出了新方法与目前已有方法的测量结果对比,表明该方法具有广阔的应用前景.     

The application of photo-conductors as voltage variable operational elements in iterative analogue computation†

This paper is concerned with the application of photo-conductors as variable operational resistor elements in iterative analogue computation. Suitable control circuits have been devised which achieve a linear relationship between a controlling voltage level and the resistance of the variable operational element. The use of crystal lumps in conjunction with silicon photo-detectors enables control circuit settling times of the order of 180 µsec to be achieved and results indicate that with the correct choice of detector, the speed of the controlled response is limited only by the performance of the operational amplifier in the control circuit.     

Power-conscious test synthesis and scheduling

BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and test scheduling affect power dissipation and present new power-conscious algorithms.