基于CPUfreq的DVFS节能技术的研究与实现

针对目前计算机系统普遍存在的功耗较大的问题,研究和实现了基于CPUfreq的DVFS节能软件;首先,分析和比较了计算机系统现有主要的功耗管理框架;然后,阐述了CPUfreq子系统及其框架结构,并基于CPUfreq子系统开发了DVFS节能软件,实现了对计算机CPU的动态电压频率调节(DVFS);最后,以720 p视频播放为应用实例,对使用DVFS节能软件后的计算机系统进行功耗测试;测试结果表明,DVFS节能软件可以实现对以PC为代表的计算机系统的初步节能。     

在异构系统上基于权重和复制的调度算法

动态电压和频率扩展技术（DVFS）的发展使异构系统可以实现低功耗，然而DVFS通过降低处理器的执行频率来降低功耗，大大增加了处理器临时故障风险，应用的可靠性受到极大威胁。针对先前算法在任务调度过程中容易出现调度失败的问题，提出一种基于权重和复制的调度算法（SAWR），以在异构系统上完成应用调度，满足并行应用的可靠性目标，同时降低系统功耗。仿真结果表明，与先前的算法相比，所提算法可以实现良好的性能。     

交互式系统下基于任务重要性的DVFS技术

动态电压频率调节技术(DVFS)是从软件层面进行系统功耗管理的重要技术。本论文针对交互式系统的特点,首先分析了当前使用的 DVFS 策略的不足之处,然后提出并实现了一种适用于交互式系统的 DVFS 策略。该策略在保障用户体验的前提下对移动设备进行功耗优化。实验结果证明,对于大多数应用能达到10%以上的功耗优化效果,部分应用最高有超过30%的功耗降低。     

商用处理器上针对能耗优化的DVFS调节机制

针对动态电压频率调节(DVFS)对应用程序运行时性能与功耗的影响,基于区间划分方法,使用现有商用处理器提供的性能监测单元,提出一种考虑访存延迟变化的DVFS性能预测模型,并利用该模型实现针对能耗优化的DVFS调节机制(eDVFS)。实验结果表明,与Linux内核提供的ondemand调节策略相比,该eDVFS调节机制能够获得最大23%、平均6.85%的能耗优化。     

基于系统调用短序列的软件漏洞检测方法研究

软件受到攻击后将在所执行的系统调用状况中有所体现,因此可将基于系统调用的入侵检测技术应用于软件漏洞的检测。本文针对无源码的可执行程序,引入系统调用节点和系统调用上下文信息的概念来刻画软件行为的动态特性和漏洞的位置信息,利用改进的STIDE算法构造软件正常行为特征库来检测并定位漏洞。实验结果表明该方法能够准确获取软件行为信息,且具有较强的漏洞检测能力。     

基于DVFS感知与虚拟机动态合并的云数据中心能效策略

为了解决云数据中心资源分配时能耗与性能间的均衡问题,提出了一种基于DVFS感知与虚拟机动态合并的能效优化策略。首先,策略通过新的DVFS管理算法（DVFS-perf）在不降低系统性能的同时降低了数据中心功耗,然后,通过频率感知的虚拟机VM部署合并算法（Frequency-aware Placement）在实现DVFS最优配置的同时最小化总体能耗,同时确保了虚拟机映射时的QoS保障。最后,通过真实云负载数据流构建仿真实验进行了性能分析。结果表明,在动态负载条件下,策略可以在不降低QoS和不增加SLA违例的情况下,降低虚拟机迁移次数和数据中心的总体能耗,更好地实现能耗与性能的均衡。     

利用OpenCV实现在Android系统下的人脸检测

本文提出一种基于开源计算机视觉库 OpenCV（Open Source Computer Vision）实现 Android 系统下人脸检测的方法。简单介绍了开发环境搭建以及利用 Android 程序框架实现此应用程序的过程,同时详细阐述了利用 JNI（Java Native Interface）调用 OpenCV 相关函数的具体步骤,以及采用 Android NDK（Native Development Kit）生成共享库的关键过程。实验结果表明此 Android 应用程序人脸检测功能性能良好。     

基于动态行为和特征模式的异常检测模型

该文针对现有的异常检测方法大多只关注系统调用出现的频率或者局部变化的情况，提出了一种将动态行为和全局特征结合起来的检测模型（DBCPIDS）．文章针对满足支持度要求的系统调用短序列，给出了特征模式的概念，并以此为基础提出了基于改进的隐马尔科夫方法（IHMM）．当利用该模型进行检测时，首先用程序轨迹匹配特征模式，如果不匹配再用IHMM进行检测，从而使得该检测模型充分利用了程序正常运行的全局特征和程序运行期间的局部变化．通过实验表明，利用该模型进行异常检测，具有很高的检测率和较低的误报率．     

基于程序的异常检测研究综述

以程序正常行为描述方法为线索,将利用系统调用数据检测程序异常行为的各种技术分类为基于规范的方法、基于频率的方法、控制流分析方法、数据流分析方法。详细介绍了这些方法的基本思想、使用的各种模型以及最新研究进展,指出并分析了现有技术中存在的问题和不足,正式提出了基于程序的异常检测技术应该以各种服务器程序为研究对象的观点,介绍了一个经过初步实验验证了的、基于服务器程序运行踪迹层次结构的异常检测原型系统,该原型系统利用了服务器程序请求一应答式工作特征和一些关键系统调用的语义信息以及运行时的动态信息,通过结构模式识别技术在识别服务器程序正常行为过程中发现异常并具备分析异常、提供入侵相关详细信息的能力,而这种能力正是异常检测技术进一步研究发展的方向之一。     

中芯国际发布65纳米标准单元库

1月21日，中芯国际宣布发布三套自主设计的65纳米标准单元库的初始版本。该单元库包括一套高性能的超高速（VHS）单元库，一套密度和速度优化的高速（HS）单元库，以及高速单元库的功耗管理工具包（PMK）。这些单元库提供了一系列的技术优势以及设计创新，包括提供多种驱动和功能的单元，对时序和功耗进行了广泛的特征化，以及对密度、速度和功耗的优化。     

User-Driven Frequency Scaling

We propose and evaluate user-driven frequency scaling (UDFS) for improved power management on processors that support dynamic voltage and frequency scaling (DVFS), e.g, those used in current laptop and desktop computers. UDFS dynamically adapts CPU frequency to the individual user and the workload through a simple user feedback mechanism, unlike currently-used DVFS methods which rely only on CPU utilization. Our UDFS algorithms dramatically reduce typical operating frequencies while maintaining performance at satisfactory levels for each user. We evaluated our techniques through user studies conducted on a Pentium M laptop running Windows applications. The UDFS scheme reduces measured system power by 22.1%, averaged across all our users and applications, compared to the Windows XP DVFS scheme     

Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors

Energy consumption has been one of the most critical issues in the Chip Multiprocessor (CMP). Using the Dynamic Voltage and Frequency Scaling (DVFS), a CMP system can achieve a balance between the performance and the energy-efficiency. In this paper, we propose a three-phase discrete DVFS algorithm for a CMP system dedicated to applications where the period of the applications’ task graph is smaller than the deadline of tasks. In these applications, multiple task graphs are unrolled and then concatenated together to form a new task graph. The proposed DVFS algorithm is applied to the newly formed task graph to stretch tasks’ execution time, lower operating frequencies of processors and achieve the system power efficiency. Experimental results show that the proposed algorithm reduces the energy dissipation by 25% on average, compared to previous DVFS approaches.     

Automatic runtime frequency-scaling system for energy savings in parallel applications

Although high-performance computing has always been about efficient application execution, both energy and power consumption have become critical concerns owing to their effect on operating costs and failure rates of large-scale computing platforms. Modern processors provide techniques, such as dynamic voltage and frequency scaling (DVFS) and CPU clock modulation (called throttling), to improve energy efficiency on-the-fly. Without careful application, however, DVFS and throttling may cause a significant performance loss due to system overhead. This paper proposes a novel runtime system that maximizes energy saving by selecting appropriate values for DVFS and throttling in parallel applications. Specifically, the system automatically predicts communication phases in parallel applications and applies frequency scaling considering both the CPU offload, provided by the network-interface card, and the architectural stalls during computation. Experiments, performed on NAS parallel benchmarks as well as on real-world applications in molecular dynamics and linear system solution, demonstrate that the proposed runtime system obtaining energy savings of as much as 14 % with a low performance loss of about 2 %.     

Managing power constraints in a single-core scenario through power tokens

Current microprocessors face constant thermal and power-related problems during their everyday use, usually solved by applying a power budget to the processor/core. Dynamic voltage and frequency scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, the continuous increase of leakage power due to technology scaling along with low resolution of DVFS makes it less attractive as a technique to match a predefined power budget as technology goes to deep-submicron. In this paper, we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy-efficiency of the processor. We will predict the processor power dissipation at cycle level (power token throttling) or at a basic block level (basic block level mechanism), using the dissipated power translated into tokens to select between different power-saving microarchitectural techniques. We also introduce a two-level approach in which DVFS acts as a coarse-grain technique to lower the average power dissipation towards the power budget, while microarchitectural techniques focus on removing the numerous power spikes. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed over the power budget, than only using DVFS to match a predefined power budget.     

基于线性预测的移动终端LPDVFS策略

针对以Linux为内核的移动操作系统,提出一种细粒度的DVFS策略LPDVFS。该策略基于历史数据,使用线性预测的方法,指导电压频率调整方向和幅度。线性预测中的参数通过回归方法确定。实验结果表明,LPDVFS策略相比Linux内核默认使用的粗粒度调频策略,能降低系统13.55%的功耗,延长移动终端的续航时间。     

Understanding the future of energy-performance trade-off via DVFS in HPC environments

DVFS is a ubiquitous technique for CPU power management in modern computing systems. Reducing processor frequency/voltage leads to a decrease of CPU power consumption and an increase in the execution time. In this paper, we analyze which application/platform characteristics are necessary for a successful energy-performance trade-off of large scale parallel applications. We present a model that gives an upper bound on performance loss due to frequency scaling using the application parallel efficiency. The model was validated with performance measurements of large scale parallel applications. Then we track how application sensitivity to frequency scaling evolved over the last decade for different cluster generations. Finally, we study how cluster power consumption characteristics together with application sensitivity to frequency scaling determine the energy effectiveness of the DVFS technique.     

Effectiveness Analysis of DVFS and DPM in Mobile Devices

The demand for high-performance embedded processors in multimedia mobile electronics is growing and their power consumption thus increasingly threatens battery lifetime.It is usually believed that the dynamic voltage and frequency scaling (DVFS) feature saves significant energy by changing the performance levels of processors to match the performance demands of applications on the fly.However,because the energy efficiency of embedded processors is rapidly improving,the effectiveness of DVFS is expected to change.In this paper,we analyze the benefit of DVFS in state-of-the-art mobile embedded platforms in comparison to those in servers or PCs.To obtain a clearer view of the relationship between power and performance,we develop a measurement methodology that can synchronize time series for power consumption with those for processor utilization.The results show that DVFS hardly improves the energy efficiency of mobile multimedia electronics,and can even significantly worsen energy efficiency and performance in some cases.According to this observation,we suggest that power management for mobile electronics should concentrate on adaptive and intelligent power management for peripheral devices.As a preliminary design,we implement an adaptive network interface card (NIC) speed control that reduces power consumption by 10% when NIC is not heavily used.Our results provide valuable insights into the design of power management schemes for future mobile embedded systems.     

动态时间片缩放:一种优化Linux 任务公平性的方法

处理器动态电压频率调节技术,对Linux系统中并发任务的性能产生不同程度的变化,从而影响并发任务计算资源分配的公平性.提出了一种利用动态时间片缩放来优化任务公平性的方法,并基于Linux操作系统任务调度程序,加入动态时间片缩放模块,该模块通过读取CPU性能监控计数器,在线计算时间片缩放系数,并利用该系数对任务时间片长度进行动态缩放.实验表明,这种方法以较小的系统开销为价,极大地提高了Linux中并发任务计算资源分配的公平性.     

Exploiting dynamic micro-architecture usage in gate sizing

Modern high performance microprocessors incorporate an abundance of replicated structural components. Many of these components often experience substantially lower utilization while executing a diverse pool of applications. To recover energy efficiency from the lower utilization, system architects resort to dynamic voltage frequency scaling (DVFS). In this paper, we demonstrate that dynamic adaptations using DVFS are markedly energy inefficient than techniques that design circuits ground up for lower performance. We propose a novel microarchitecture aware gate sizing and threshold voltage assignment algorithm to mitigate this current limitation. Our technique is the first of its kind that exploits architectural slack in gate sizing, and leverages on-chip redundancy and slack. We evaluate this circuit-architectural co-optimization framework in a superscalar processor by combining standard cell based gate sizing flows with state-of-the-art architectural simulation. Our results show 17-46% improvement in the datapath energy efficiency over traditional circuit designs incorporating DVFS schemes.