Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

基于控制K次平方根非门的类Toffoli门构造方法

在量子电路综合算法中,由于非置换量子门比置换量子门具有更复杂的规则,直接使用非置换量子门会大幅度提高综合算法的复杂性,因此可先使用非置换量子门生成相应的置换量子门,然后再用这些置换量子门综合所求量子可逆逻辑电路,从而提高算法性能。本文重点研究如何用非置换量子门构造新的置换量子门,为此吸收了格雷码的思想,提出了一种高效的递归构造方法,实现使用控制非门和控制K次平方根非门(非置换量子门),快速生成最优的类Toffoli门(置换量子门)。     

On figures of merit in reversible and quantum logic designs

Five figures of merit including number of gates, quantum cost, number of constant inputs, number of garbage outputs, and delay are used casually in the literature to compare the performance of different reversible or quantum logic circuits. In this paper we propose new definitions and enhancements, and identify similarities between these figures of merit. We evaluate these measures to show their strength and weakness. Instead of the number of gates, we introduce the weighted number of gates, where a weighting factor is assigned to each quantum or reversible gate, based on its type, size and technology. We compare the quantum cost with weighted number of gates of a circuit and show three major differences between these measures. It is proved that it is not possible to define a universal reversible logic gate without adding constant inputs. We prove that there is an optimum value for number of constant inputs to obtain a circuit with minimum quantum cost. Some reversible logic benchmarks have been synthesized using Toffoli and Fredkin gates to obtain their optimum values of number of constant inputs. We show that the garbage outputs can also be used to decrease the quantum cost of the circuit. A new definition of delay in quantum and reversible logic circuits is proposed for music line style representation. We also propose a procedure to calculate the delay of a circuit, based on the quantum cost and the depth of the circuit. The results of this research show that to achieve a fair comparison among designs, figures of merit should be considered more thoroughly.      

Towards quantum reversible ternary coded decimal adder

Quantum ternary logic is a promising emerging technology for the future quantum computing. Ternary reversible logic circuit design has potential advantages over the binary ones like its logarithmic reduction in the number of qudits. In reversible logic all computations are done in an invertible fashion. In this paper, we propose a new quantum reversible ternary half adder with quantum cost of only 7 and a new quantum ternary full adder with a quantum cost of only 14. We termed it QTFA. Then we propose 3-qutrit parallel adders. Two different structures are suggested: with and without input carry. Next, we propose quantum ternary coded decimal (TCD) detector circuits. Two different approaches are investigated: based on invalid numbers and based on valid numbers. Finally, we propose the quantum realization of TCD adder circuits. Also here, two approaches are discussed. Overall, the proposed reversible ternary full adder is the best between its counterparts comparing the figures of merits. The proposed 3-qutrit parallel adders are compared with the existing designs and the improvements are reported. On the other hand, this paper suggested the quantum reversible TCD adder designs for the first time. All the proposed designs are realized using macro-level ternary Toffoli gates which are built on the top of the ion-trap realizable ternary 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.     

Synthesis of reversible circuits with minimal costs

We present fast algorithms to synthesize exact minimal reversible circuits for various types of gate and cost. By reducing reversible logic synthesis problems to permutation group problems, we use the powerful algebraic software GAP to solve such problems. Our approach can minimize for arbitrary cost functions of gates. In addition, we show that Peres gates are a better choice than the standard Toffoli gates in libraries of universal reversible gates. This work was supported by the NNSF of China under Grant 60773205 and the Fund of Cultivating Leading Scholars in UESTC.     

基于正反控制门的可逆网络化简

提出并证明正反控制(PNC)门级联电路中的合并、移动和分解规则,利用此规则给出基于PNC门的可逆网络的化简算法。根据移动规则对门序列进行正向和反向双向扫描,寻找符合化简条件的两门,直到可逆网络不发生变化为止。所有3变量可逆函数上的实验结果表明,该算法能减少PNC门级联网络的门数和控制位数,降低可逆网络的代价。     

On security of image ciphers based on logic circuits and chaotic permutations

This paper introduces a cryptanalysis of image encryption techniques that are using chaotic scrambling and logic gates/circuits. Chaotic scrambling, as well as general permutations are considered together with reversible and irreversible gates, including XOR, Toffoli and Fredkin gates. We also investigate ciphers based on chaotic permutations and balanced logic circuits. Except for the implementation of Fredkin’s gate, these ciphers are insecure against chosen-plaintext attacks, no matter whether a permutation is applied globally on the image or via a block-by-block basis. We introduce a new cipher based on chaotic permutations, logic circuits and randomized Fourier-type transforms. The strength of the new cipher is statistically verified with standard statistical encryption measures.     

Design and analysis of area efficient QCA based reversible logic gates

The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

Upper bounds for reversible circuits based on Young subgroups

We present tighter upper bounds on the number of Toffoli gates needed in reversible circuits. Both multiple controlled Toffoli gates and mixed polarity Toffoli gates have been considered for this purpose. The calculation of the bounds is based on a synthesis approach based on Young subgroups that results in circuits using a more generalized gate library. Starting from an upper bound for this library we derive new bounds which improve the existing bound by around 77%.