基于简单网络断层扫描的失效链路定位研究

失效链路是无线传感器网络中一种典型的网络故障现象,严重影响了无线传感器网络的运行与服务质量,必须加以发现并修复。主要研究了基于简单网络断层扫描方法定位失效链路的技术。引入二元分离模型描述链路状态,在已知链路状态先验分布条件下,失效链路定位问题描述为最大后验估计问题。通过将失效链路定位问题映射为加权最小集合覆盖问题,提出了一种基于启发策略的失效链路定位算法。仿真实验结果表明,该算法具有可行性和有效性。     

基于双端口RNI的容错NoC架构

为解决片上网络中故障路由器与IP核的通信问题,设计一种低硬件开销的双端口资源网络接口,在传统2D-mesh结构基础上,通过添加部分链路,将每个IP核连接到2个路由器上,并针对该架构设计相应的容错路由算法。实验结果表明,该方案硬件开销较小、容错能力较强。     

A fault-tolerant pipelined architecture for symmetric block ciphers

Secure transmission over wired/wireless networks requires encryption of data and control information. For high-speed data transmission, it would be desirable to implement the encryption algorithms in hardware. Faults in the hardware, however, may cause interruption of service. This paper presents a simple technique for achieving fault tolerance in pipelined implementation of symmetric block ciphers. It detects errors, locates the corresponding faults, and readily reconfigures during normal operation to isolate the identified faulty modules. Bypass links with some extra pipeline stages are used to achieve fault tolerance. The hardware overhead can be controlled by properly choosing the number of extra stages. Moreover, fault tolerance is achieved with negligible time overhead.     

基于NPV广义超立方体最佳容错路由算法

在网络可靠性研究中,设计较好的容错路由策略、尽可能多地记录系统中最优通路信息,一直是一项重要的研究工作.超立方体系统的容错路由算法分为可回溯算法和无回溯算法.一般说来,可回溯算法的优点是容错能力强:只要消息的源节点和目的节点有通路,该算法就能够找到把消息传递到目的地的路径;其缺点是在很多情况下传递路径不能按实际存在的最短路径传递.其代表是深度优先搜索(DFS)算法.无回溯算法是近几年人们比较关注的算法.该算法通过记录各邻接节点的故障信息,给路由算法以启发信息,使消息尽可能按实际存在的最短路径传递.这些算法的共同缺点是只能计算出Hamming距离不超过n的路由.在n维超立方体系统连通图中,如果系统存在大量的故障,不少节点对之间的最短路径大于n,因此,这些算法的容错能力差.提出了一个实例说明采用上述算法将遗失60%的路由信息.另外,由于超立方体的结构严格,实际中的真正超立方体系统不多.事实上,不少的网络系统可转换为具有大量错误节点和错误边的超立方体系统.因此,研究能适应具有大量错误节点和错误边的超立方体系统的容错路由算法是一个很有实际价值的工作.研究探讨了:(1) 定义广义超立方体系统;(2) 在超立方体系统中提出了节点通路向量(NPV)概念及其计算规则;(3) 提出了中转点技术,使得求NPV的计算复杂度降低到O(n);(4) 提出了基于NPV的广义超立方体系统最佳容错路由算法(OFTRS),该算法是一种分布式的和基于相邻节点信息的算法.由于NPV记录了超立方体系统全部最优通路和次最优通路的信息,在具有大量故障的情况下,它不会遗漏任何一条最优通路和次最优通路信息,从而实现了高效的容错路由.在这一点上,它优于其他算法.     

Fault-tolerant ring embedding in a star graph with both link andnode failures

The star graph interconnection network has been recognized as an attractive alternative to the hypercube network. Previously, the star graph has been shown to contain a Hamiltonian cycle. In this paper, we consider an injured star graph with some faulty links and nodes. We show that even with f_e⩽n-3 faulty links, a Hamiltonian cycle still can be found in an n-star, and that with f_v⩽n-3 faulty nodes, a ring containing at most 4f_v nodes less than that in a Hamiltonian cycle can be found (i.e. the ring contains at least n!-4f_v nodes). In general, in an n-star with f_e faulty links and f_v faulty nodes, where f_e+f_v⩽n-3, our embedding is able to establish a ring containing at least n!-4f_v nodes     

新型联想记忆神经网络的硬件实现研究

论文研究了一种新型联想记忆神经网络的硬件实现,并给出了运行框图及其说明。每个神经元由一个功能简单的微处理单元和一组存储单元构成,存储在连接中的数据,转移到相应的目标神经元的E2PROM中,由一个微处理器控制所有神经元的运行和作为与外部设备的接口,硬件网络本身同时实现了回忆和记忆功能。     

Distributed computing on oriented anonymous hypercubes with faulty components

We give efficient algorithms for distributed computation on oriented, anonymous, asynchronous hypercubes with possible faulty components (i.e. processors and links) and deterministic processors. Initially, the processors know only the size of the network and that they are inter-connected in a hypercube topology. Faults may occur only before the start of the computation (and that despite this the hypercube remains a connected network). However, the processors do not know where these faults are located. As a measure of complexity we use the total number of bits transmitted during the execution of the algorithm and we concentrate on giving algorithms that will minimize this number of bits. The main result of this paper is an algorithm for computing Boolean functions on anonymous hypercubes with bit cost , where is the number of faulty components (i.e. links plus processors), is the number of links which are either faulty, or non-faulty but adjacent to faulty processors, and is the diameter of the hypercube with faulty components. Received: October 1992 / Accepted: April 2001     

一种基于无效链路的分布式故障诊断一致性协议

故障诊断一致性(fault diagnosis agreement,FDA)是高可靠容错分布式系统的性能和完整性的重要保障.目前,大部分FDA协议还是只考虑单一故障组件的简单网络,而对于实际的分布式应用、故障节点和故障链路并存的系统假设更加有意义.但是,在此假设下,对恶意(拜占庭故障)组件的诊断是不可能满足FDA的.为此,首先提出了一种无效链路(invalid link)故障模型,可以更加准确地描述恶意组件的故障行为对系统的影响,有效提高故障诊断的覆盖率.在此模型基础上,提出了一个基于证据的故障诊断协议--PLFDA,可以同时对恶意节点和恶意链路进行检测和定位,并且能够满足故障诊断一致性要求.     

基于多链路故障的网络切片生存性算法

为了保证当底层网络的多条物理链路发生故障时用户业务能够不间断,提出一种基于多链路故障的网络切片生存性算法。通过区分切片上承载的业务类型,当高可靠低延迟切片请求到达后,将物理节点按节点重要度排序后进行映射,再对故障链路采用多备份路径算法,选取带宽资源消耗最少的路径依次对故障链路进行重映射,当高带宽切片请求到达后,采用广度优先搜索的节点映射算法,再通过多备份路径对故障链路进行恢复。仿真结果表明,该算法能够提高切片平均映射成功率、长期平均收益开销比、物理链路利用率和故障恢复率,缩短平均故障恢复时延。     

A fault tolerant routing algorithm based on cube algebra for hypercube systems

We propose an approach to determine the shortest path between the source and the destination nodes in a faulty or a non-faulty hypercube. The number of faulty nodes and links may be rather large and if any path between the nodes exists, the developed algorithm determines it. To construct this algorithm, some properties of the cube algebra are considered and some transformations based on this algebra are developed.     

片上网络中面向链路故障的容错路由方法研究

片上网络在工业和学术领域越来越受欢迎,但是晶体管显著缩小后可靠性不足问题给片上网络带来严峻挑战。传统的容错路由算法通过使报文绕过故障区域,因此可以克服链路或路由器故障。但是这些方法会增加报文延时,并在故障区域周围产生拥塞。本文利用两个虚拟信道提出一种新的容错路由方法,它通过确定每个虚拟信道哪些转向被允许和禁止,使得一个虚拟信道中被禁止的转向在另一信道被允许。当发生链路故障时,该方法基于一种新的故障信息传播机制使报文在最短路径上传输。另外,通过充分利用网络中的所有被允许转向对本文方法进行扩展,以支持多链路故障。最后的仿真实验也验证了本文方法的有效性。     

A Fault-Tolerant and Heuristic Routing Algorithm for Faulty Hypercubes

A fault-tolerant and heuristic routing algorithm for faulty hypercube systems is described.To improve the efficiency,the algorithm adopts a heuristic backtracking strategy and each node has an array to record its all neighbors‘ faulty link information to avoid unnecessary searching for the known faulty links.Furthermore,the faulty link information is dynamically accumulated and the technique of heuristically searching for optimal link is used.The algorithm routes messages through the minimum feasible path between the sender and receiver if at least one such path exists,and takes the optimal path with higher probability when faulty links exist in the faulty hypercube.     

Byzantine agreement in the presence of mixed faults on processorsand links

In early stage, the Byzantine agreement (BA) problem was studied with single faults on processors in either a fully connected network or a nonfully connected network. Subsequently, the single fault assumption was extended to mixed faults (also referred to as hybrid fault model) on processors. For the case of both processor and link failures, the problem has been examined in a fully connected network with a single faulty type, namely an arbitrary fault. To release the limitations of a fully connected network and a single faulty type, the problem is reconsidered in a general network. The processors and links in such a network can both be subjected to different types of fault simultaneously. The proposed protocol uses the minimum number of message exchanges and can tolerate the maximum number of allowable faulty components to make each fault-free processor reach an agreement     

Adding multiple-fault tolerance to generalized cube networks

Generalized cube networks are limited to single-fault tolerance with respect to permutation connections. The vector space approach presented here yields many fault-tolerance schemes that can tolerate two and three faults. In each scheme, redundant switches and links are added to networks and interconnected in certain ways. These redundancies are represented by a matrix called the redundancy matrix. A fault-free network without redundancy is represented by an identity matrix. As faulty switches and links are discovered, the remaining switches and links are remapped to establish an intact network. The remapping is analogous to converting an invertible redundancy matrix back to an identity matrix     

Reaching fault diagnosis agreement on an unreliable general network

Recently, Siu et al. failed in their attempt to use the FDAMIX protocol to eliminate the fault diagnosis agreement (FDA) problem with mixed faults on the processors in a general network. Therefore, in this study, a new protocol, the FDAL protocol, is introduced to solve the FDA problem with mixed faults on the links. The FDAL is capable of detecting/locating faulty links to reconfigure the unreliable general network into a reliable network, and is able to increase the system performance and strengthen network integrity.     

Design and implementation of highly reliable dual-computer systems

Two of the main parameters of real-time computer systems are reliability and performance. Researchers are always looking for solutions to increase the values of these parameters, which is the goal of this study. To this end, we propose an architecture for a dual-computer system that operates in real-time with fault tolerance implemented purely by hardware. The hardware, as designed and implemented, performs the following key services: 1) determination of the fault type (temporary or permanent) and 2) localization of the faulty computer without using self-testing techniques or diagnostic routines. Our design has several benefits: 1) the designed hardware shortens the recovery point time period; 2) the proposed nontrivial sequence of fault-tolerant services reduces (to two) the number of logical segments that must be re-run to recover computational processes; and 3) the determination of the fault type allows for the elimination of only computers with permanent faults. These contributions yield improvements in both the performance and reliability of the system.     

Bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architectures using Particle Swarm Optimization

This research paper proposes a bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architecture using particle swarm optimization (PSO), which considers synchronous, asynchronous, and self-organizing communication mechanisms to intelligently load-balance the traffic on the entire network in the presence of faulty components. By way of experimentation and simulation, this study demonstrates that the proposed scheme can converge to a global optimum, minimal routing path in real time, in the presence of network congestion and faulty routers and links. The basic PSO algorithm was improved to implement the proposed routing scheme, named bio-inspired self-aware fault-tolerant routing protocol (BISFTRP). This scheme uses the synchronous, asynchronous, and self-organizing features of PSO to create a global routing table and intelligent adaptation, which gives rise to scalable, real-time, and dynamic routing decisions with high throughput, low latency, and minimum power consumption. A cycle-accurate simulation system to demonstrate the flexibility and efficiency of the proposed scheme is used. Comparison results with state-of-the-art fault-tolerant routing algorithms show that the BISFTRP routing protocol achieves high routing performance without routing oscillations and throughput degradation. Furthermore, the hardware implementation results show that the BISFTRP router achieves an efficient area and power utilization, compared with state-of-the-art routers.     

深度网络模型压缩综述

深度网络近年在计算机视觉任务上不断刷新传统模型的性能,已逐渐成为研究热点.深度模型尽管性能强大,然而由于参数数量庞大、存储和计算代价高,依然难以部署在受限的硬件平台上（如移动设备）.模型的参数一定程度上能表达其复杂性,相关研究表明并不是所有的参数都在模型中发挥作用,部分参数作用有限、表达冗余、甚至会降低模型的性能.本文首先对国内外学者在深度模型压缩上取得的成果进行了分类整理,依此归纳了基于网络剪枝、网络精馏和网络分解的方法;随后,总结了相关方法在多种公开深度模型上的压缩效果;最后,对未来研究可能的方向和挑战进行了展望.     

Modular neuron comprises of memristor-based synapse

Design of analog modular neuron based on memristor is proposed here. Since neural networks are built by repetition of basic blocks that are called neurons, using modular neurons is essential for the neural network hardware. In this work modularity of the neuron is achieved through distributed neurons structure. Some major challenges in implementation of synaptic operation are weight programmability, weight multiplication by input signal and nonvolatile weight storage. Introduction of memristor bridge synapse addresses all of these challenges. The proposed neuron is a modular neuron based on distributed neuron structure which it uses the benefits of the memristor bridge synapse for synaptic operations. In order to test appropriate operation of the proposed neuron, it is used in a real-world application of neural network. Off-chip method is used to train the neural network. The results show 86.7 % correct classification and about 0.0695 mean square error for 4-5-3 neural network based on proposed modular neuron.

     

An efficient modular spare allocation scheme and its application tofault tolerant binary hypercubes

Consideration is given to fault tolerant systems that are built from modules called fault tolerant basic blocks (FTBBs), where each module contains some primary nodes and some spare nodes. Full spare utilization is achieved when each spare within an FTBB can replace any other primary or spare node in that FTBB. This, however, may be prohibitively expensive for larger FTBBs. Therefore, it is shown that for a given hardware overhead more reliable systems can be designed using bigger FTBBs without full spare utilization than using smaller FTBBs with full spare utilization. Sufficient conditions for maximizing the reliability of a spare allocation strategy in an FTBB for a given hardware overhead are presented. The proposed spare allocation strategy is applied to two fault tolerant reconfiguration schemes for binary hypercubes. One scheme uses hardware switches to replace a faulty node, and the other scheme uses fault tolerant routing to bypass faulty nodes in the system and deliver messages to the destination node