An efficient method of determining functional equivalence classes of a network with reconvergent fan-out

This paper is a study of the effects of the faults on tho functional operation of a combinational logic circuit. The conditions whereby two different faults can produce tho sancio functional output arc investigated. In this approach two fault graphs of the circuits arc drawn. By manipulating these fault graphs the faults which are functionally equivalent can be obtained. An algorithm for determining the functionally equivalent classes of faults in a combinational circuit is presented. The unique feature of the algorithm is that it produces tho true functional equivalence (not structural equivalence) even for the circuit with reconvergent fan-out with unequal parity.     

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits.     

基于多故障模型的并发测试生成方法

精简测试向量集是解决电路测试问题的一种行之有效的方法。针对故障电路,采用多故障模型方法可以简化有多个单故障的电路,且保持电路功能完整。论文在结构分析的基础上,利用多故障模型寻找故障集中的并发故障,建立并发关系图,并运用分团的思想对故障集中的并发故障进一步划分,以获得故障集的并发测试集。与传统的方法相比,并发测试生成将获得更加精简的测试向量集。     

基于混沌搜索的数字电路多故障测试生成

针对数字电路中多故障测试生成较难的问题,本文提出了基于混沌搜索的数字电路多故障测试生成算法。该算法先把多故障转换成为单故障,再用神经网络的方法对单故障电路构造故障的约束网络,最后用混沌搜索方法求解故障约束网络能量函数的最小值点获得原电路中多故障的测试矢量。在一些国际标准电路上的实验结果表明了本算法的可行性。     

A comprehensive fault diagnosis technique for reversible logic circuits

Fault diagnosis is a complex and challenging problem in reversible logic circuits. The paper proposes a novel fault diagnosis technique for missing control faults in reversible logic circuits. The main focus of this technique is to extract the unique fault signature for each missing control fault in the circuit. The fault signatures are the sequences of test vectors to identify the location of the faults. Based on these fault signatures a unique fault diagnosis tree is built. Our proposed fault diagnosis algorithm is used to traverse the fault diagnosis tree to find the presence and location of the fault. The traversal process is simple and fast. The algorithm executes in linear time and experimental results for benchmark circuits show the reduction of test patterns compared to earlier works.     

模糊聚类与SVM诊断模拟电路单软故障的方法

针对低可测性模拟电路中存在的模糊组问题,提出一种模拟电路单个软故障诊断的方法．该方法对被测电路的故障进行模糊聚类,根据聚类的有效性指标自适应确定聚类数,并利用聚类的信息来确定可测元件集,引入支持向量机对故障进行分类识别．支持向量机结构简单、泛化能力强．最后,以模拟和混合信号测试标准电路证实了文中方法的有效性．     

使用逻辑锥分割的组合电路等价性验证

为了提高等价性验证在数字电路中的验证效率,提出一种逻辑锥分割和可满足性相结合的方法。通过划分规则把参照电路和实现电路划分成若干个逻辑锥,利用匹配技术对两者的逻辑锥进行匹配,将已匹配的两个逻辑锥的输出用一个异或门连接,从而得到Miter电路,将该结构转换成相应的合取范式,用可满足性引擎来验证Miter电路是否功能等价。在ISCAS’85基准电路的实验结果表明该方法的可行性。     

P＋P：同步时序电路的并行码和并行故障模拟器

开发的一个新的快速故障模拟器Ｐ＋Ｐ。该模拟器使用了并行码与并行故障模拟算法，实现了同步时序电路故障模拟的两路并行性，采用了全局故障分组，锥形操作，电路级化及改进的组号ＩＤ等技术。Ｐ＋Ｐ已在ＳＵＮ ＳＰＡＲＣ－２工作站上实现，运行了大部分的ＩＳＣＡＳ Ｂｅｎｃｈｍａｒｋ同步时序电路。最后给出了实验结果。     

Genetically Evolved Neural Networks for Fault Classification in Analog Circuits

A new fault classification system for analog circuits is presented. The proposed system utilises the pattern recognition potential of neural networks and the population-based search strategy of genetic algorithms in detecting and isolating faults in analog circuits. Features that characterise the circuit behaviour under fault-free and fault situations are first simulated or measured. An unsupervised fault-grouping algorithm that estimates the overlaps between different faults in the features space is then introduced. Accordingly, a suitable training set is constructed and employed to train a population of genetically evolved neural networks to recognise circuit faults. A two-phase analog fault classification strategy is also developed. Experimental results demonstrate the high classification accuracy of the proposed system. ID="A1" Correspondence and offprint requests to: M.A. El-Gamal, Department of Engineering Physics Mathematics, Cairo University, Giza, Egypt Email: mhgamal@alpha1-eng.cairo.eun.eg     

全速电流测试的故障精简和测试生成

针对全速电流测试方法测试生成算法效率低下的问题，提出故障压缩、故障模拟等故障精简的方法，以提高该方法的测试生成效率．实验结果表明，该方法使得需要进行测试生成的故障点平均减少了66．8％，该测试方法的测试生成的效率提高了200多倍．     

基于DCCA-IWO-MKSVM的模拟电路故障诊断方法

为了提高模拟电路故障的诊断效果,提出基于DCCA-IWO-MKSVM的模拟电路故障诊断方法。采用DCCA算法对模拟电路的故障特征进行提取,构造新的融合特征。对支持向量机的核函数进行线性组合构造新的多核函数,并用IWO算法对其参数进行优化,以构建最优故障诊断模型,用于融合特征的学习分类。故障诊断实验结果表明:对于融合特征的故障诊断效率,该算法要优于单核函数的IWO-SVM算法,且整个故障诊断系统的诊断效果具有较高的准确率。     

量子逻辑电路中控制点失效错误的定位

确保可逆电路的正确性与可靠性,错误检测必不可少,错误定位难度更高.通过分析发现当可逆电路中规模为k的可逆门发生控制点失效时仅对2<'n-k>个输入向量的输出产生影响,据此给出了一种把当前错误集分成若干个子集的方法生成控制点失效错误定位树.传统的错误定位方法都是通过生成真值表和错误表来产生错误定位树;该方法不需要生成和存储真值表以及错误表就能够有效定位电路中控制点失效错误.与Rfault算法相比,空间复杂度和时间复杂度更小,算法效率更高,能应用于更大规模的电路.     

基于蚂蚁路径的时序电路故障诊断算法

提出了一种VLSI时序电路自动测试型生成(Automatic test pattern generation，ATPG)的新算法。传统ATPG算法采用局部状态转换图或收集门级电路的知识以及提取电路规则来解决时序电路ATPG的困难。本算法引入新的模型，着重解决了ATPG中的计算冗余问题。在蚂蚁路径模型的基础上，前向搜索得到了重建，故障点的前向传输和回溯归结到了单一路径之上．而该路径上可能分布着许多待测的故障点，从而改善了以往时序电路ATPG算法中搜索重复而导致的计算冗余问题，同时，最小测试向量的获取为数学定理所证明。最后在Benchmark电路上进行的与ILP算法的比较试验表明，本算法具备同样的故障覆盖率，且速度更快。     

基于多特征信息融合的模拟电路故障预测

为解决利用单一信息进行故障预测的不足以及提高模拟电路故障预测的准确度,提出了一种将信息融合应用到模拟电路故障预测中的方法.提取模拟电路多个测点的多种故障特征量,对其进行时间序列分析,采用ARMA模型研究其预测过程,将得到的预测结果转换为模拟电路故障发生的概率,最后将得到的多个数据进行加权融合,实现了基于多特征信息融合的...     

Reliability characteristics of quadratic Hebbian-type associativememories in optical and electronic network implementations

The performance capability of quadratic Hebbian type associative memories (QHAM's) in the presence of interconnection faults is examined, and equations for predicting the probability of direct convergence P(dc) given a fraction of interconnection faults are developed. The interconnection faults considered are the equivalent of open circuit and short circuit synaptic interconnections in electronic implementations. Our results show that a network with open circuit interconnection faults has a higher probability of direct convergence P (dc) than a network with short circuit interconnection faults, when the fraction of failed interconnections p is small and the short circuit signal G is large. Certain values of G are found to have only mild effects on network performance degradation. Network reliability characteristics taking the generalization capability into account are also analyzed. All of these results are compared with those of Hebbian type associative memories (HAM's), which have linear association network models. Our results indicate that QHAM's have much higher network capacity and fault tolerance capability in the presence of interconnection faults. However, the fault tolerance to input errors in QHAM's is much less than that of HAM's.     

同步时序电路测试生成研究

本文分析了固定故障所反映出的状态变换特征，提出状态变换故障模型。基于无复位时序电路，详细研究了有复位的同步电路测试生成问题及在无复位电路中的应用。最后讨论了故障精简以及启发知识在测试过程中的应用。     

Fault isolation in analog circuits using a fuzzy inference system

This paper introduces a fuzzy inference system (FIS) for single analog fault diagnosis. The ability of fuzzy logic to encode structured knowledge in a numerical framework is exploited in isolating faults in analog circuits. A training set that simulates the behaviour of the circuit due to a set of anticipated single faults as well as the fault-free situation is first constructed. For each anticipated fault, this set relates the circuit measurements to the corresponding deviation in the faulty circuit element from its nominal. These measurements and the deviations in circuit elements are both fuzzified into appropriate linguistic fuzzy values. A fuzzy rule base for each fault that characterizes the circuit response by linking symptoms to causes is built. The outputs of the fuzzy rule bases are then defuzzified to recover crisp values for the deviations in circuit elements. A fault diagnosis procedure that utilizes the proposed FIS is also presented along with a brief analysis and comparison with a number of existing artificial intelligence-based techniques. A test example that demonstrates the potential of this procedure in fault isolation is illustrated.     

基于斜率故障模型的模拟电路软故障字典法

提出了一种新的模拟电路故障字典法。与传统方法不同,该方法利用两个节点电压之间的关系函数作为故障特征。对于线性模拟电路,节点电压关系函数为一次函数,函数的斜率可以作为故障模型,同时可以诊断硬故障和参数(软)故障。由于模拟电路存在容差,最小直线距离法可以用于处理电路中的容差问题。     

Can large fanin circuits perform reliable computations in the presence of faults?

For ordinary circuits with a fixed upper bound on the fanin of its gates it has been shown that logarithmic redundancy is necessary and sufficient to overcome random hardware faults (noise). Here, we consider the same question for unbounded fanin circuits which in the fault-free case can compute Boolean functions in sublogarithmic depth. Now the details of the fault model become more important. One may assume that only gates, resp. only wires may deliver wrong values, or that both gates and wires may behave faulty. The fault tolerance depends on the types of gates that are used, and whether the error probabilities are known exactly or only an upper bound for them. Concerning the first distinction the two most important models are circuits consisting of and- and or-gates with arbitrarily many inputs, and circuits built from the more general type of threshold gates. We will show that in case of faulty and/or-circuits as well as threshold circuits an increase of fanin and size cannot be traded for a depth reduction if the error probabilities are unknown. Gates with large fanin are of no use if errors may occur. Circuits of arbitrary size, but fixed depth can compute only a tiny subset of all Boolean functions reliably. Only in case of threshold circuits and exactly known error probabilities redundancy is able to compensate faults. We describe a transformation from fault-free to fault-tolerant circuits that is optimal with respect to depth keeping the circuit size polynomial.