适于图像解压的离散余弦逆变换快速算法

讨论了离散余弦变换(DCT)的基本图像的特性以及实际图像数据的特点,提出了利用基本图像进行二维8×8离散余弦逆变换(IDCT)的快速算法.新算法通过三个技术降低二维8×8IDCT的运算量(1)利用基本图像的对称性;(2)把反量化过程和IDCT融为一步;(3)利用实际图像数据的特点绝大多数量化后的变换系数为零值且非零系数中又有许多的值为±1.理论分析表明,三种技术的融合可大大减少计算量.以多幅标准图像为样本数据,对新方法和当前最有影响的Feig算法做了比较,结果表明文中算法的乘法次数降了约60%,加法次数降了约15%.     

矢量基二维离散余弦变换

本文提出一种频率抽取(DIF)矢量基二维离散余弦变换(2D DCT)快速算法。该算法将H.S.HOU的一维离散余弦变换(ID DCT)递归快速算法推广到二维,利用三角恒等式cos(α+β)=2cosαcosβ—cos(α—β),得出数值稳定的二维离散余弦变换快速矢量基算法。其数值稳定性比Haque提出的矢量基2D DCT算法要好,和常用的行列算法相比节省25%乘法运算量。文中给出了算法流图。     

基于DCT的DMT系统设计与峰均功率比研究

提出一种新的基于离散余弦变换(Discrete cosin transform,DCT)及其逆变换的离散多音调制系统实现方案,利用IDCT/DCT变换替代IFFT/FFT变换实现多载波信号的调制与解调,并对该系统的峰均功率比(Peakto average power ratio,PAPR)进行了理论分析。在此基础上,提出一种利用离散余弦变换能量集中特性降低系统PAPR的方法,与基于选择性映射算法的离散多音调制系统(SLM-FFT-DMT)相比,基于DCT的DMT系统比SLM-FFT-DMT系统的PAPR低1.5dB,且具有计算法复杂度低的优点。     

一种HEVC标准中IDCT变换的FPGA实现

为降低新一代高效视频编码(HEVC)标准中解码端多尺寸逆离散余弦变换(Inverse Discrete Cosine Transform,IDCT)中的资源消耗,设计了一种IDCT硬件电路结构。通过使用现场可编程门阵列(Field-Programmable Gate Array,FPGA)内部嵌入式RAM单元进行矩阵转置运算,从而减少了对内部寄存器的使用。对IDCT系数矩阵进行分解得到不同尺寸下的统一运算电路结构,利用流水线技术实现对运算单元的加速,同时采用并行数据调度减少数据处理等待时间。设计结果表明,设计吞吐量为3.6点/时钟周期,满足了4k×2k@30 f/s视频信号的实时处理需求。     

基于PCI总线的IP仿真验证平台的WDM驱动程序设计

该文介绍了在Windows2000/XP下,开发基于PCI总线的IP仿真验证平台的WDM设备驱动程序和应用程序的基本方法,以DCT/IDCT(逆离散余弦变换)的IP为例给出平台的实际应用。并指出广泛使用的开发工具DriverStu-dio2.7的一些严重漏洞。     

基于快速二维离散余弦变换算法的人脸特征提取

离散余弦变换(DCT)具有图像信号处理后对图像显示效果影响不明显的优点。本文针对离散余弦变换(DCT)系数在人脸识别中的应用,研究不同的DCT块进行编码后其系数对图像质量和识别结果的影响,提出利用快速2D-DCT(二维离散余弦变换)代替普通DCT的人脸特征提取方法。该方法可以使得在对人脸进行平均分割后的图像块处理时间大大减少,从而能够在同样的时间内提取更多的DCT系数用于人脸识别。实验结果表明,该方法快速而且是有效的。     

基于视频会议系统的DCT和Inverse-DCT算法研究及实现

视频图像压缩是视频会议系统能否提供良好性能的关键技术之一.要想最大限度地利用有限的网络带宽,在视频图像传输前,必须在不严重降低图像质量的前提下,采用合适的压缩编码算法对视频图像进行压缩.离散余弦变换DCT(Discrete Cosine Transform)被认为是优秀的视频图像压缩算法之一.首先,以视频会议系统应用为背景,简单介绍了DCT和反向离散余弦变换IDCT(InverseDCT)算法、公式及其相关;其次,以VC++为工具,以个人笔记本电脑为平台,实现了DCT和IDCT算法,给出并且分析了部分应用程序代码;最后,做了视频图像压缩的仿真实验.     

二维离散分数余弦变换的改进形式

将一维离散余弦变换的变换核扩展到二维分数形式,得到Pei形式的二维离散分数余弦变换。通过整数阶余弦变换的线性叠加构造一种改进形式的二维离散分数余弦变换,并基于特征值和特征向量理论,分析2种离散分数余弦变换的周期关系。数值仿真结果表明,2种形式可以达到相同的变换结果,适用于图像编码、数字水印等领域。     

计算q~(l_1)×q~(l_2)二维DCT的快速算法

离散余弦变换 (DCT)广泛应用于信号处理的许多领域 ,多维 DCT(MD- DCT)是图像处理和视频信号处理的重要工具 .通常 ,多维 DCT采用行列法用一维算法实现 ,实现效率较低 .近年来虽然出现了一些多维 DCT直接实现算法 ,但大多要求变换为 2 n× 2 n,限制了适用范围 .该文研究较一般的二维 DCT快速算法 ,将 ql1 × ql2 (q为奇素数 ;l1 ,l2 分别为两个不同的整数 )二维 DCT转化为多项式变换和一维简化余弦变换 ,通过特别设计的快速多项式变换算法和 1D- RDCT递归分解算法 ,提出了一种计算复杂性较低且具有规则运算结构的 ql1 × ql2 二维 DCT算法 .本算法的设计方法可以方便地推广到多维 (>2 )的情况 .     

面向龙芯平台的快速DCT算法及其实现

针对龙芯2E平台不能流畅播放视频文件的问题,对视频变换过程进行优化,采用一种新的离散余弦变换（DCT）算法,基于龙芯2E多媒体指令集对其进行实现,用该算法替代FFmpeg软件中的DCT算法。测试结果表明,新的DCT算法性能比传统DCT算法提高近11倍,优化后的FFmpeg软件编码速度提高10％左右。     

Low power design of DCT and IDCT for low bit rate video codecs

This paper examines low power design techniques for discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuits applicable for low bit rate wireless video systems. The techniques include skipping DCT computation of low energy macroblocks, skipping IDCT computation of blocks with all coefficients equal to zero, using lower precision constant multipliers, gating the clock, and reducing transitions in the data path. The proposed DCT and IDCT circuits reduce power dissipation by, on average, 94% over baseline reference circuits.     

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

The 3D discrete cosine transform and its inverse (3D DCT/IDCT) extend the spatial compression properties of conventional 2D DCT to the spatio-temporal coding of 2D videos. The 3D DCT/IDCT transform is particularly suited for embedded systems needing the low-complexity implementation of both video encoder and decoder, such as mobile terminals with video-communication capabilities. This paper addresses the problem of real-time and low-power 3D DCT/IDCT processing by presenting a context-aware fast transform algorithm and a family of VLSI architectures characterized by different levels of parallelism. Implemented in submicron CMOS technology, the proposed hardware macrocells support the real-time processing of main video formats (up to high definition ones with an input rate of tens of Mpixels/s) with different trade-offs between circuit complexity, power consumption and computational throughput. Voltage scaling and adaptive clock-gating strategies are applied to reduce the power consumption versus the state of the art.     

基于行列变换结构的2-DCT/IDCT的误差分析

提出一种新的基于行列变换结构的2-DCT／IDCT误差模型。利用该模型得到的计算2-DCT／IDCT的误差公式，能够告知2-DCT／IDCT结构各部件的字长对整体计算的误差贡献。本文根据该误差模型，具体计算了基于行列变换结构的既符合IDCT有穷字长标准，又能够尽可能降低硬件开销的2-DCT／IDCT各部件字长，为所有采用该类结构的设计提供了参照。     

一种用于MPEG的IDCT算法

离散余弦变换（ＤＣＴ）及其逆变换（ＩＤＣＴ）广泛应用于图像编码系统中，在本文中，我们提出了一种针对ＭＰＥＧ特点的ＩＤＣＴ的实现算法，根据ＭＰＥＧ中ＤＣＴ系数的分布特性和ＩＤＣＴ算法的对称性质，我们可以采用同一运算结构计算不同的频率分量，从而减小系统的实现复杂度，测试结果表明，当采用该算法时，在运算速度下降约１４％的情况下，ＩＤＣＴ的ＶＬＳＩ实现规模约下降为１／３。     

A 160 Mpixel/s IDCT processor for HDTV

The architecture and characteristics of a fully functional 40 MHz device that performs the 8×8 inverse discrete cosine transform (IDCT) for digital HDTV decoders are presented. The IDCT chip converts four 14-b DCT coefficients into four 11-b pixel values each cycle. Fixed-coefficient multiplier Wallace trees in which partial products are rounded before summation help compute the inner products. The 31000-gate device was implemented in a 10.5 mm die using 1 μm CMOS array-based process     

Reduction of discrete cosine transform/ quantisation/inverse quantisation/inverse discrete cosine transform computational complexity in H.264 video encoding by using an efficient prediction algorithm

This study develops a novel prediction algorithm to effectively save the computational complexity of discrete cosine transform (DCT), quantisation (Q), inverse Q (IQ), and inverse DCT (IDCT) in video encoding for H.264 applications. Based on the DC value of the DCT coefficients that is equal to the sum of residual data in the 4times4 sub-macroblock (sub-MB), a mathematical model is built to develop a prediction algorithm for reducing the computations in the DCT/Q/IQ/IDCT process. Experimental results and comparisons demonstrate that the proposed prediction algorithm significantly reduces the encoding time while incurring little additional overhead, and lowers the bit rate with little peak signal-to-noise ratio degradation.     

视频编码的并行处理

在视频压缩中存在大量可并行的计算如DCT/IDCT、运动估计、运动补偿、量化/反量化等,它们占计算量的主要部分,特别是DCT和运动估计,成为视频压缩处理的瓶颈,因此必须研究适应视频压缩处理的并行算法。文章就DCT和运动估计在SIMD(单指令多数据)的处理器PIII上算法实现的方法,进行具体研究。     

AVS标准中整数DCT变换快速算法的硬件设计

介绍了AVS标准中整数DCT变换矩阵的化简方法,该方法提高了一维整数DCT变换硬件实现的速度。基于此一维整数DCT变换,采用模块复用和流水线设计,实现了二维整数DCT直接变换在一个时钟周期内完成,工作频率可达160MHz。仿真结果证实了该算法的有效性。     

Recursive algorithm, architectures and FPGA implementation of the two-dimensional discrete cosine transform

A new recursive algorithm and two types of circuit architectures are presented for the computation of the two-dimensional discrete cosine transform (2D DCT). The new algorithm permits to compute the 2D DCT by a simple procedure of the 1D recursive calculations involving only cosine coefficients. The recursive kernel for the proposed algorithm contains a small number of operations. Also, it requires a smaller number of pre-computed data compared with many of existing algorithms in the same category. The kernel can be easily implemented in a simple circuit block with a short critical delay path. In order to evaluate the performance improvement resulting from the new algorithm, an architecture for the 2D DCT designed by direct mapping from the computation structure of the proposed algorithm has been implemented in an FPGA board. The results show that the reduction of the hardware consumption can easily reach 25% and the clock frequency can increase 17% compared with a system implementing a recently reported 2D DCT recursive algorithm. For a further reduction of the hardware, another architecture has been proposed for the same 2D DCT computation. Using one recursive computation block to perform different functions, this architecture needs only approximately one-half of the hardware that is required in the first architecture, which has been confirmed by an FPGA implementation.