基于FPGA的混沌信号发生器的设计与实现

提出了基于FPGA设计混沌信号发生器的改进方法.采用Euler算法将连续混沌系统转换为离散混沌系统;基于IEEE-754单精度浮点数标准和模块化设计理念,使用Quartus Ⅱ软件,采用VHDL和原理图相结合的方式设计混沌信号发生器.最后,在FPGA实验系统上进行实验,在示波器上显示了混沌吸引子的相图及时域混沌信号.由于采用了基于数据选择器的面积优化方法,复用耗费逻辑资源较多的浮点运算模块,大大减少了混沌信号发生器所占用的FPGA逻辑资源.实验结果表明了该方法的有效性和通用性.     

在LonWorks网络中使用浮点数据

Neuron C是一种专门为Neuron芯片设计的程序设计语言.它在ANSI C的基础上进行了扩展,是开发LonWorks应用的有力工具.Neuron C不直接支持ANSI C中浮点数的算术和比较运算,但是它提供了一个浮点函数库,从而允许使用符合IEEE 754标准的浮点数.文中详细介绍了Neuron C中浮点数据类型的定义、浮点常量的生成方法和浮点函数库的使用.通过一个实例LonWorks网络,演示了浮点数据的使用.     

在LonWorks网络中使用浮点数据

Neuron C是一种专门为Neuron芯片设计的程序设计语言。它在ANSIC的基础上进行了扩展，是开发LonWorks应用的有力工具。Neuron C不直接支持ANSIC中浮点数的算术和比较运算，但是它提供了一个浮点函数库，从而允许使用符合IEEE754标准的浮点数。文中详细介绍了Neuron C中浮点数据类型的定义、浮点常量的生成方法和浮点函数库的使用。通过一个实例LonWorks网络，演示了浮点数据的使用。     

基于IEEE 754的浮点数存储格式分析研究

浮点数的表示和存储直接影响计算机的结构和性能,IEEE754是浮点运算部件事实上的工业标准,是计算机上使用最为广泛的浮点标准。文章在阐述了浮点数的基本概念和IEEE754浮点数的表示形式及其格式的基础上,比较深入的比较、分析和研究了Intelx86和SPARC结构计算机上使用的三种IEEE浮点数的存储格式。     

基于C8051F120的PI控制过程的快速运算

在控制系统的校正过程中,使用了增量式PI算法。在分析系统过程后,考虑到在PI校正中运算量集中在浮点数的乘法,运算速度有提升空间。为了提高校正程序运算速度,设计一种基于增量式PI算法的浮点数运算程序,将浮点数运算转化为整数乘法和移位,利用C8051 F120中的MACO(乘法和累加引擎),实现整数乘法和移位的快速运行。分析算法速度,运算时间缩短到原时间的27%。根据系统实际情况,分析数据运算精度,控制增量误差小于1%,能够保证系统控制精度,并得到实验验证。快速运算方法能够满足控制要求,硬件成本低,缩短了单周期内系统运算时间。     

正交匹配追踪算法的优化设计与FPGA实现

设计了一种基于FPGA的正交匹配追踪(Orthogonal Matching Pursuit,OMP)算法的硬件优化结构,对OMP算法进行了改进,大大减少了乘法运算次数;在矩阵分解部分采用了交替柯列斯基分解(Alternative Cholesky Decomposition,ACD)方法避免开方运算,以减小计算延迟,整个系统采用并行计算、资源复用技术,在提高运算速度的同时减少资源利用。在Quartus II开发环境下对该设计进行了RTL级描述,在Altera公司的Cyclone II EP2C70F672C6上进行综合并完成时序仿真,仿真结果验证了设计的正确性。     

数字图像DCT变换的FPGA实现

图像DCT变换由于计算量大,软件实现往往难以满足实时处理的要求,基于FPGA在硬件上实现了图像的DCT变换。设计采用了2D-DCT的行列分解结构,在两级1D-DCT之间引入双RAM结构,通过乒乓操作保证了前后级DCT运算的并行性,提高了运算速度。整个模块使用Verilog HDL建模,通过ModelSim编写激励对逻辑功能进行了验证,最后在Quartus II上通过了综合编译,设计优化后下载到Altera EP2C70F896C6芯片上进行实现。结果显示,该模块功能结构正确,可作为一个独立单元集成在图像的实时处理系统中。     

模糊控制器中高速除法器的FPGA设计

为选择适用于FPGA硬件实现的模糊控制器中除法器的设计方案,分别采用LPM方法、不恢复余数移位减法和查找表法进行了设计和比较,给出了满足实时性和速度与资源平衡的设计方案。本设计基于Altera公司FPGA Cyclone II系列EP2C5Q208C7芯片,利用VHDL和Quartus II软件完成编译、仿真和下载和调试。该设计方法具有通用性,可生成IP核并适于高速运算场合。     

一种新型的基于FPGA的SMS4密码算法电路设计

提出一种新型的基于FPGA硬件实现的SMS4分组密码算法电路设计。相对于常用的流水线设计方法和迭代设计方法,此设计将流水线和迭代运算相结合,结合了前者较高处理速度和后者较小实现面积的优点,达到了较好的性能,对WLAN商用密码算法的FPGA硬件实现有参考意义。通过Quartus II 8.0软件时序仿真验证了此设计的正确性,并使用以Cyclone II FPGA芯片为核心的DE2开发板验证了此设计的可实现性。     

C语言中浮点数的表示范围浅析

浮点数是C语言中的一种数据类型,但在标准C中并没有给出其具体的描述,即数的存储格式及表示范围。部分经典的C语言程序设计教程中给出了浮点数的表示范围,但存在不严谨和值得商榷的地方。结合IEEE754标准,就C语言中浮点数内在存储格式进行分析并给出结论。     

浮点开方运算单元的电路设计

文章提出了一种基于逐位循环开方算法,"四位一开方"的浮点开方运算单元的电路设计方案,使限制周期时间的循环迭代部分的门级数降低到14级。按14级门延时为周期时间计算,完成一个IEEE单、双精度浮点数的开方运算分别需要15和29周期。同时,文章对目前开方运算所采用的两类主要的算法-逐位循环开方算法和牛顿－莱福森迭代开方算法进行了描述,其中包括数的冗余表示等内容。     

嵌入式系统中48位高精度浮点类型的设计与实现

本文参考IEEE754标准,用无符号整型定义48位高精度浮点类型,详细给出了48位浮点类型与无符号32位整型相互转化及加减乘除的实现方法和流程图。算法已在ATMEL 89C55和PIC16F877中通过测试,并在基于SST9—三轴加速度传感器的控制处理中得到应用。     

基于RISC-V浮点指令集FPU的研究与设计

针对目前浮点运算软件实现速度慢,不能满足嵌入式处理器实时性要求以及运算种类有限等问题,提出了一种基于RISC-V指令集的浮点处理器,能够执行加法、减法、乘法、除法、平方根、乘累加以及比较运算,完全符合IEEE 754-2008标准。在VCS仿真环境下对浮点处理器进行了功能验证,各模块均能满足正确性要求。将浮点处理器与一款开源处理器核蜂鸟E203集成,使用SMIC 0.18工艺库完成了逻辑综合,并在FPGA上对设计进行了测试。结果表明,该浮点处理器的逻辑门数仅为24 200,吞吐量为150 MFLOPS,与已公开文献的设计方案相比,硬件面积分别减少7%、1.5%。综合运行频率可达100 MHz。     

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.     

基于FPGA的IEEE802.11协议帧生成器的设计

IEEE 802.11, the most popular standard, defines the protocols which covers all of Ethernet based wireless communication. This paper presented an implementation of IEEE 802.11 Frame Generator, which used FPGA as a hardware platform. This generator constructs the 802.11 frame and supplied it to DSSS as signal to be sent. There are 3 modules in this design. The 1st is the global control module, the 2nd module is CRC- 32 check and the 3rd is used to produce frame serial number. The characteristic of this de- sign is that the signal process and the transmission are made at the same time, i.e. real time processing. That is important to the wireless network device, which has narrower bandwidth and lower process energy. The Verilog HDL codes, block diagram of the whole system, and the simulation results were described in this paper.     

Formal Verification of the <Emphasis Type="Italic">VAMP</Emphasis> Floating Point Unit

We report on the formal verification of the floating point unit used in the VAMP processor. The dual-precision FPU is IEEE compliant and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions.We have formalized the IEEE standard 754. The formalization is supplemented by a rich theory of rounding, which includes notations and theorems facilitating the verification of the actual hardware. The theory of rounding enables the separation of the hardware into smaller modules which can be verified individually. Each module is verified on the gate level against a formal specification. The combination of these formal specifications, together with the theorems from the theory of rounding, yield the overall correctness of the FPU, i.e., theorems stating that the gate-level hardware complies with the high-level formalization of the IEEE standard. The verification is done completely in the theorem prover PVS.We further report on the implementation and test of the verified FPU on a Xilinx FPGA.     

Standardization and testing of implementations of mathematical functions in floating point numbers

Requirements definition and test suites development for implementations of mathematical functions in floating point arithmetic in the framework of the IEEE 754 standard are considered. A method based on this standard is proposed for defining requirements for such functions. This method can be used for the standardization of implementations of such functions; this kind of standardization extends IEEE 754. A method for designing test suites for the verification of those requirements is presented. The proposed methods are based on specific properties of the representation of floating point numbers and on some features of the functions under examination.     

基于FPGA的可配置浮点向量乘法单元设计实现

针对目前采用IEEE 754浮点标准设计的FPGA浮点运算器中吞吐率与资源利用率低等问题,提出一种运算精度与运算器数量可配置的并行浮点向量乘法运算单元。通过浮点运算器的指数、尾数位数可配置化设计,提高系统资源利用率,并将流水线技术与并行结构结合,提高数据吞吐率。以EP4CE115型FPGA为测试平台,当配置10组FP14运算器时,系统的逻辑资源占用约为4.2%,峰值吞吐率可达4.5 GFLOPS。结果表明,提出的浮点向量乘法单元有效提高了FPGA资源利用率与运算吞吐率,同时具有高度的可移植性与通用性,适用于FPGA向量乘法运算的加速。     

HW/SW for an intelligent transducer network based on IEEE 1451 standard

This work describes a hardware/software co-design system development, named IEEE 1451 platform, to be used in process automation. This platform intends to make easier the implementation of IEEE standards 1451.0, 1451.1, 1451.2 and 1451.5. The hardware was built using NIOS II processor resources on Alteras Cyclone II FPGA. The software was done using Java technology and C/C++ for the processors programming. This HW/SW system implements the IEEE 1451 based on a control module and supervisory software for industrial automation.     

VelociTI结构浮点DSPs寄存器堆读写的流水线设计

研究了VelociTI结构浮点数字信号处理器寄存器堆的流水线读写原理并提出了一种设计方法。该方法对单操作数双精度浮点指令采用2个32位数据通路用1个流水线周期读取源操作数，双操作数双精度浮点指令采用锁定译码单元，利用若干流水线周期读取源操作数。采用写控制向量的方法实现了流水线多个周期执行写操作。该方法正确实现了基于IEEE754标准的双精度浮点数据在寄存器堆与功能单元之间的32位数据通路上的传输，仿真结果验证了其正确性。