Vertical Mirror Fabrication Combining KOH Etch and DRIE of (110) Silicon

This paper presents fabrication of MEMS-actuated optical-quality vertical mirrors as the key active optical components in a silicon optical bench (SOB) technology. The fabrication process is based on a combination of potassium hydroxide (KOH) etch and deep reactive ion etching (DRIE) of (110) SOI wafers. The process starts by creating optical-quality vertical surfaces by KOH etch, followed by an oxidation step to protect them. The patterned wafer is then etched by DRIE to define actuators. The process is designed to allow the KOH etch and DRIE to be independently optimized without compromising either while at the same time meeting the challenge of lithography on high-aspect-ratio structures. Three variations of the fabrication process are demonstrated, two that use double masking layers and one that uses a silicon masking layer. We demonstrate in-plane scanners and fast translational vertical mirrors fabricated using these processes. In addition, we propose extensions of the fabrication process to account for DRIE aspect-ratio limitations. Mask layouts of key SOB building blocks, including vertical mirrors, beam splitters, and parallel-plate actuators, are also presented.$hfill$ [2008-0146]      

Real-time etch-depth measurements of MEMS devices

An in situ, real-time process control tool was developed for MEMS deep reactive-ion etch (DRIE) fabrication. DRIE processes are used to manufacture high-aspect-ratio silicon structures up to several hundred microns thick, which would be difficult or impossible to produce by other methods. DRIE MEMS technologies promise to deliver new devices with increased performance and functionality at lower cost. A major difficulty with DRIE is the control of etch depth. Our research shows that it is possible to monitor the etch depth of various MEMS structures (holes, pillars, trenches, etc.) through measurement and analysis of the infrared reflectance spectrum. Depths as large as 150 μm have been measured. Excellent correlation is found between the etch depths determined by analysis of these measurements and those measured with an SEM. In addition to etch depth, other parameters such as the photoresist thickness (e.g., mask erosion) can be simultaneously extracted. Based on these results, an infrared-reflectance etch monitor was integrated onto a reactive ion etcher at the Berkeley Sensor and Actuator Center for real-time monitoring and end-point determination. The integrated optical metrology system demonstrated accurate real-time monitoring of the etch depth and photoresist mask erosion     

Micromachined flat-walled valveless diffuser pumps

The first valveless diffuser pump fabricated using the latest technology in deep reactive ion etching (DRIE) is presented. The pump was fabricated in a two-mask micromachining process in a silicon wafer polished on both sides, anodically bonded to a glass wafer. Pump chambers and diffuser elements were etched in the silicon wafer using DRIE, while inlet and outlet holes are etched using an anisotropic etch. The DRIE etch resulted in rectangular diffuser cross sections. Results are presented on pumps with different diffuser dimensions in terms of diffuser neck width, length, and angle. The maximum pump pressure is 7.6 m H₂O (74 kPa), and the maximum pump flow is 2.3 ml/min for water     

Fabrication of micro-trench structures with high aspect ratio based on DRIE process for MEMS device applications

The micro-trench structures with high aspect ratio based on the single crystal silicon substrate are fabricated via the deep reactive ion etching (DRIE) process at different etching patterns. The relationship between the micro-trench structures and the DRIE etching patterns is investigated by simulating and processing. The micro-trench structures are obtained to meet the requirements of some MEMS devices for special applications. The profile roughness and micro-trench structures are observed by the atomic force-microscope and the field emission scanning electron microscopy. The verticality (V) of micro-trench structures is average 0.19 in the oxygen environment. The micro-trench structures exhibit better verticality, less roughness and better stability than that of no oxygen. The scalloping effects gradually decreased and the profile becomes more and more polished.     

Factorial experimental design applied to DRIE for optimised process in power electronics applications requiring high-aspect ratio trenches

A reliable factorial experimental design was applied to DRIE for specifically producing high-aspect ratio trenches. These trenches are to be used in power electronics applications such as active devices: deep trench superjunction MOSFET (DT-SJMOSFET) and passive devices: 3D integrated capacitors. Analytical expressions of the silicon etch rate, the verticality of the profiles, the selectivity of the mask and the critical loss dimension were extracted versus the process parameters. The influence of oxygen in the passivation plasma step was observed and explained. Finally, the analytical expressions were applied to the devices objectives. A perfectly vertical trench 100-μm deep was obtained for DT-SJMOSFET. Optimum conditions for reaching high-aspect ratio structures were determined in the case of high-density 3D capacitors.     

Towards a versatile DRIE: silicon pit structures combined with electrochemical etch stop

A novel approach for fabricating low-pitch arrays of silicon membranes on standard CMOS wafers by combining deep-reactive ion etching (DRIE) and electrochemical etching (ECE) techniques is presented. These techniques have been used to fabricate membrane-based sensors and sensor arrays featuring different membrane sizes on a single wafer with a well defined etch stop. The described procedure is particularly useful in cases when the usage of SOI wafers is not an option. The combination of a grid-like mask pattern featuring uniform-size etch openings for the DRIE process with a reliable ECE technique allowed to fabricate silicon membranes with sizes ranging from 0.01 mm/sup 2/ to 2.2 mm/sup 2/. The development of this new method has been motivated by the need to design a compact n-well-based calorimetric sensor array, where the use of a standard ECE technique would have significantly increased the overall size of the device.     

Miniaturization of Electrostatic Fluid Accelerators

Existing thermal-management methods for electronics do not meet the technology needs and remain a major bottleneck in the evolution of computing, sensing, and information technology. The decreasing size of microelectronic components and the resulting increasing thermal output density require novel cooling solutions. Electrostatic fluid accelerators (EFAs), also known as electrohydrodynamic ionic wind pumps, have the potential of becoming a critical element of electronic thermal-management solutions. In order to take full advantage of EFA-based thermal management, it is essential to miniaturize EFA technology. This paper demonstrates the successful operation of a mesoscale microfabricated silicon EFA. Several cantilever structures fabricated in bulk silicon with radii of tip curvature ranging from 0.5 to 25 mum are used as the corona electrode. The device was fabricated using the combination of deep reactive ion etching (DRIE) and reactive ion etch (RIE) microfabrication processes. Forced convection cooling is demonstrated using infrared imaging, showing a 25degC surface temperature reduction over an actively heated substrate. The fabrication and test results of a mesoscale microfabricated EFA are presented in this paper.     

Bulk micromachining fabrication platform using the integration of DRIE and wet anisotropic etching

This study presents a bulk micromachining fabrication platform on the (100) single crystal silicon substrate. The fabrication platform has employed the concept of vertical corner compensation structure and protecting structure to integrate the wet anisotropic etching and DRIE processes. Based on the characteristics of wet anisotropic etching and DRIE, various MEMS components are demonstrated using the bulk micromachining platform. For instance, the free suspended thin film structures and inclined structures formed by the {111} crystal planes are fabricated by the wet etching. On the other hand, the mesas and cavities with arbitrary shapes and the structures with different leve l heights (or depths) are realized by the characteristics of DRIE. Since the aforementioned structures can be fabricated and integrated using the presented fabrication platform, the applications of the bulk micromachining processes will significantly increase.This research is based on the work supported by WALSIN LIHWA Corporation and the National Science Council of Taiwan under grant of NSC-91–2218-E-007–034. The authors would like to thank the Central Regional MEMS Research Center of National Science Council, Semiconductor Research Center of National Chiao Tung University and National Nano Device Laboratory for providing the fabrication facilities.     

Fabrication of Integrated Vertical Mirror Surfaces and Transparent Window for Packaging MEMS Devices

A scheme for creating metal-coated vertical mirrors in silicon, along with an integrated transparent package lid for assembling, packaging, and testing microelectromechanical systems (MEMS) devices is presented. Deep reaction ion etching (DRIE) method described here reduces the loading effect and maintains a uniform etch rate resulting in highly vertical structures. A novel self-masking lithography and liftoff process was developed to ensure that the vertical mirrors undergo uniform metallization while leaving a transparent window for optical probing. Front side of a Si wafer was shallow-etched using DRIE to define an eventual optical window. This surface was then anodically bonded to a Pyrex wafer. Backside Si was then patterned to define thin channels around the optical window. These channels were vertically etched using DRIE, after which the unattached portions of the window region were removed. Negative photoresist was spun on the remaining vertical structures and the stack was exposed from the Pyrex side using Si structures as a self-mask. Subsequent metal sputtering and liftoff results in the metallized top and mirror sidewalls while leaving a clear window. These integrated mirrors and lids are then bonded to the active MEMS mirrors. Various processes and results are illustrated with an example of packaged corner cube retroreflectors (CCRs)     

Hole-type two-dimensional photonic crystal fabricated in silicon on insulator wafers

We report the realization of two-dimensional (2D) photonic crystal (PhC) holes array using synthesized processing techniques of deep UV lithography, time-multiplexed reactive ion etching (TMRIE) and focus ion beam (FIB) etching. In this study, mixed density of holes and waveguide patterns of 2D PhC structures was first formed in silicon on insulator wafers through use of a scanner. Ultra wide grooves were then defined, aligned to the deep submicron size devices. Following deep etching of more than 50 μm by TMRIE, PhC structures were then revealed for device etching. Such design of fabrication process allows realization of disparate pattern dimensions and also etching depths. Through avoidance of etch lag effect, notching of devices at interface of device silicon and buried oxide layer was avoided. At the same time, through a singular FIB etch in the final step of the process following buried oxide release for PhC structures on critical dimension structures, severe loading effects of such structures were avoided to enable a wide process window of lithography and etch.     

Effect of process parameters on the surface morphology andmechanical performance of silicon structures after deep reactive ionetching (DRIE)

The ability to predict and control the influence of process parameters during silicon etching is vital for the success of most MEMS devices. In the case of deep reactive ion etching (DRIE) of silicon substrates, experimental results indicate that etch performance as well as surface morphology and post-etch mechanical behavior have a strong dependence on processing parameters. In order to understand the influence of these parameters, a set of experiments was designed and performed to fully characterize the sensitivity of surface morphology and mechanical behavior of silicon samples produced with different DRIE operating conditions. The designed experiment involved a matrix of 55 silicon wafers with radius hub flexure (RHF) specimens which were etched 10 min under varying DRIE processing conditions. Data collected by interferometry, atomic force microscopy (AFM), profilometry, and scanning electron microscopy (SEM), was used to determine the response of etching performance to operating conditions. The data collected for fracture strength was analyzed and modeled by finite element computation. The data was then fitted to response surfaces to model the dependence of response variables on dry processing conditions     

Optimal companding vector quantization for circularly symmetric sources

In this paper, it is shown that optimal Z_2 lattice vector quantization can be implemented using radial companding technique. We derive the optimal vector compressor function for radial compander of memoryless Gaussian source. This result is obtained by taking into consideration the source geometry and by establishing the relation between the volumes and the point densities at the compressor input and compressor output. We also derive the linearized model - the piecewise linear compander. Its performance closely approaches that of optimal vector quantization. For example, for R = 8 bits/dimension and L = 16 regions, the difference between corresponding distortions is about 0.037 dB, while the asymptotic performances are identical.     

Process Development for CMOS-MEMS Sensors With Robust Electrically Isolated Bulk Silicon Microstructures

This paper presents a deep reactive-ion etching (DRIE)-based post-CMOS micromachining process that provides robust electrically isolated single-crystal silicon (SCS) microstructures for integrated inertial sensors. Several process issues arise from previously reported three-axis CMOS microelectromechanical system (MEMS) accelerometers, including sidewall contaminations of SCS microstructures in plasma etch and a severe silicon undercut caused by overheating of suspended microstructures. Solutions to these issues have been found and are discussed in detail in this paper. In particular, a lumped-element model is developed to estimate the temperature rise on suspended microstructures in a silicon DRIE process. Based on the thermal modeling and experiments, a thick photoresist layer has been used as a thermal path to avoid the severe silicon undercut. The sidewall contamination problem is also eliminated using the modified CMOS-MEMS process. A three-axis accelerometer with a low-noise, low-power on-chip amplifier has been successfully fabricated using the new process. Footing effect was observed on the backside of the sensor microstructure, but it has little effect on the structural integrity and sensitivity of the sensor.     

Silicon isotropic and anisotropic etching for MEMS applications

In MEMS technology there is an increasing interest in developing high aspect ratio silicon columns having rounded corners, slightly positive tapered shafts, sharp tips, and smooth surfaces. A precise control of the profile can be used for different applications, such as for molds used in polymer hot embossing processes, micro needles used for drug delivery and blood sampling, and neural probes used for controlling motor or sensory prosthetic devices. The mixture of hydrofluoric acid (HF) and nitric acid (HNO₃) is an isotropic etchant and is used in MEMS technology to etch silicon. We present a novel way of isotropically and anisotropically etch MEMS structures using the HF–HNO₃ etchant. The shape and size of the structure is controlled by the dynamics of acid solution to yield highly repeatable and reproducible needle geometry.     

Post-CMOS processing for high-aspect-ratio integrated siliconmicrostructures

Presents a new fabrication sequence for integrated-silicon microstructures designed and manufactured in a conventional complementary metal-oxide-semiconductor (CMOS) process. The sequence employs a post-CMOS deep silicon backside etch, which allows fabrication of high aspect ratio (25:1) and flat (greater than 10 mm radius of curvature) MEMS devices with integrated circuitry. A comb-drive resonator, a cantilever beam array and a z-axis accelerometer were fabricated using this process sequence. Electrical isolation of single-crystal silicon was realized by using the undercut of the reactive ion etch (RIE) process. Measured out-of-plane curling across a 120-μm-wide 25-μm-thick silicon released plate was 0.15 μm, which is about ten times smaller than curl of the identical design as a thin-film CMOS microstructure. The z-axis DRIE accelerometer structure is 0.4 mm by 0.5 mm in size and has a 25-μm-thick single-crystal silicon proof mass. The measured noise floor is 1 mG/√Hz, limited by electronic noise. A vertical electrostatic spring "hardening" effect was theoretically predicted and experimentally verified     

Study of silicon backside damage in deep reactive ion etching for bonded silicon–glass structures

 For devices of bonded silicon and glass structures fabricated by deep reactive ion etching (DRIE), it is important to avoid damage at the silicon sidewall and backside during through-wafer etching in order to ensure reliability of devices. The silicon damage caused by charge accumulation at the glass surface is inhibited by means of an electrically conducting layer patterned onto the glass and connected with the silicon. In this study, indium tin oxide films were applied in order to identify the positions of silicon damage in the structural layout without destruction of samples. From the results, we report that there exists silicon damage caused by charge accumulation at the silicon islands divided by DRIE and we present important rules for mask layout when utilizing this method. Received: 10 August 2001/Accepted: 24 September 2001 This paper was presented at the Fourth International Workshop on high Aspect Ratio Microstructure Technology HARMST 2001 in June 2001.     

Phototransistors for CMOS Optoelectronic Integrated Circuits

Integrated pnp phototransistors (PT) built in 0.6 μm OPTO ASIC CMOS are presented. The production starts with a low doped epitaxial wafer as bulk material. This work presents several different types of phototransistors due to the realization of base and emitter areas. The different types are optimized for different goals, e.g. responsivity or bandwidth. Responsivities up to 76 A/W, 35 A/W for DC light at 675 nm and 850 nm, respectively, as well as 37.2 A/W for modulated light at 300 kHz and 850 nm wavelength were achieved. On the other hand bandwidths up to 14 MHz with lower responsivity were achieved with different design of base and emitter area. Due to the fact that the used process is a production silicon CMOS technology, cheap integration of an integrated optoelectronic circuit is possible. Possible applications are low cost, highly sensitive optical receivers, optical sensors, systems-on-a-chip for optical distance measurement or combined to an array even a 3D camera.     

一种圆片级硅三层键合的三明治加速度传感器

提出了一种利用体微机械加工技术制作的硅三层键合电容式加速度传感器.采用硅各向异性腐蚀和深反应离子刻蚀技术实现中间梁一质量块结构的制作,通过玻璃软化键合方法完成上、下电极的键合.在完成整体结构圆片级真空封装的同时通过引线腔结构方便地实现了中间电极的引线.传感器芯片大小为6.8 mm×5.6 mm×l.26 ITUTI,其中敏感质量块尺寸为3.2 mm×3.2 mm×0.42 mm.对封装的传感器性能进行了初步测试,结果表明制作的传感器灵敏度约4.15 pF/g,品质因子为56,谐振频率为774 Hz.     

Anisotropic Si deep beam etching with profile control using SF6/O2 Plasma

This paper presents the results of dry plasma etching of single crystal silicon using SF₆ and O₂ as process gases in a traditional Reactive Ion Etcher. The highly anisotropic profiles are achieved for a deep beam feature with depths in excess of 100 m. The effect of O₂ concentration on both etch rate and etch profile is investigated across a range of chamber pressures. Etch profile anisotropy can be controlled through appropriate variations in O₂ and SF₆ flow rate and SEM images are provided to show this effect over a range of chamber pressures and RF powers. Our results indicate O₂ concentration to be the primary factor influencing etch profile, while system pressure is shown to have a strong influence over etch rate. Shadowing effect also has been discussed for the possible application of releasing the freestanding beams. These results aided in the formulation of a suitable process for fabricating long-travel electrothermally actuated beam structures with the depth and width of 100 m and 20 m. The ratio of beam depth to the mask-undercut is 10:1. This etching technique is resulting in the successful fabrication of thermoelectrically-driven long-travel beam structures.The author would like to thank Professor R. R. A. Syms and Mr Michael Larsson for encouraging and useful discussions during this work. This project is supported by the EPSRC under grant GR/R07844/01.