基于XLP技术的超低功耗数据采集系统设计

针对目前便携式气体浓度数据采集仪体积大、功耗高以及功能单一等缺点,采用Microchip公司基于XLP技术的低功耗器件—PIC16F193X设计了一款多功能、小体积、低功耗的便携式数据采集仪。本文首先分析了整个系统的硬件低功耗设计原理,然后针对系统的低功耗特点,进行了低功耗的软件程序设计。整个软件采用了基于有限状态机的设计,最后对整个系统进行了低功耗特性测试,测试结果表明采用这种设计方法比传统的设计方法能延长便携式数据采集仪的工作时间6倍以上。     

STM32 L水下记录仪的软硬件低功耗设计

以水下记录仪为例,从硬件和软件两方面研究了基于STM32L系列微控制器的低功耗设计技术及本仪器所采用的方法。对系统组成及功能进行分析的基础上,设计了记录仪的低功耗策略。在硬件方面选用低功耗、高效率器件,并采用供电控制方法。在软件方面采用层次化、标准化的软件架构,减少代码冗余量。最后通过电压和电流对照实验,证明了本系统低功耗设计的有效性。     

随钻测井系统井下传感器的低功耗设计

提出了随钻测井系统井下传感器的一种低功耗设计方法。介绍了随钻测井系统,其需要在井下长时间工作且只能通过电池供电的特殊性,决定了低功耗设计是整个系统设计的核心问题。本文通过对低功耗电路设计原则的分析,结合随钻测井系统的要求,采用Freescale公司的MC9S12Q128单片机,在硬件和软件两个方面对随钻测井系统井下传感器进行了低功耗设计,采用低功率器件和动态功耗分配的省电管理模式。     

中小尺寸液晶屏图形显示控制芯片的低功耗设计

在VLSI设计中，低功耗的要求已经变得越来越重要。低功耗设计可以在不同的设计层次考虑．采用低功耗技术的层次越高，对功耗的改善越显著。本文针对一款中小尺寸液晶屏图形显示控制芯片的设计，提出了一种有效的低功耗设计方案。通过功耗分析比较表明．该设计方案极大的改善了这款芯片的功耗特性。     

一种基于低功耗单片机的供热仪表系统开发

随着国内住宅业的迅速发展,热量计在供暖行业的集中供热和分户计量中越来越重要了。本仪表的二次仪表部分为低功耗单片机系统,可以采用电池供电,极大地拓宽了热量计的应用范围。在低功耗设计时,除了在硬件上选用低功耗的芯片,还在软件上采用了低功耗设计技术。另外,本仪表还具有RS-485接口,可以在相当远的距离内和上位机通讯,便于上位机采集数据。     

基于ZigBee的温室监测系统的低功耗设计

针对传统温室大棚有线监测系统存在施工复杂、线路多和维护难等缺陷,提出了一种基于ZigBee无线传感网络技术的低功耗温室监测系统的设计方案;通过对系统各部分的能耗进行分析,结合实际情况对传感器节点采用低功耗设计策略;硬件设计上采用低功耗射频芯片和智能开关芯片,软件编写上采用事件驱动方法延长节点休眠时间;该系统能够准确采集温室内光照度、空气温湿度、土壤水分和二氧化碳浓度等环境信息,并具有低功耗、低成本和易扩展等特点;测试结果验证了该方案的可行性。     

基于MSP430的航标监控终端的实现

以辅航设备控制监测系统改进项目为背景,从航标监控系统RTU总体设计的角度出发,介绍了在航标监控管理系统中,以TI公司的MSP430低功耗芯片为核心的数据采集处理器,阐述了时间片工作方式结合MSP430芯片低功耗模式的设计,并在系统整体设计上采用电源管理模块化,使终端灵活分配电源的供应,以达到最小低功耗,设计出满足低功耗、无线监测、航道设备运行环境等功能的低功耗航标智能监控终端,测试结果表明,该监控终端具有良好的可靠性、实时性、稳定性和低功耗性.     

基于MSP430G2553的工业遥控发射器的设计

本文所设计的工业遥控发射器的射频芯片采用TI公司的CC1101,主控芯片采用TI公司最新推出的超低功耗单片机MSP430G2553,具有超低功耗、高可靠性、高性价比、稳定性能好等优点。     

IXP 2400网络处理器低功耗技术应用研究

文章从软件低功耗优化角度,结合IXP2400网络处理器中XScalecore处理器体系结构的低功耗技术特点,在SimWattch模拟平台上,就频率动态调整和程序设计语言不同结构成分对应用程序运行功耗的影响进行了模拟和分析,通过对一组Banchmark程序的模拟,结果表明在编译系统、操作系统或应用程序设计中采用这些低功耗优化技术设计可降低至少23%以上的运行功耗。     

基于低功耗技术的工业无线温度变送器

针对工业应用领域中无线传感器网络节点功耗较大的问题,以常见的温度参数测量为背景,通过在变送器节点硬件设计中采用低功耗的元器件,设计并实现一种大量程、低功耗的无线温度变送器,在节点运行机制方面采用定期休眠的方法,将变送器节点的测量范围控制在-50°C~900°C之间。实验结果表明,该低功耗方法是可行有效的。     

Leakage Minimization Technique for Nanoscale CMOS VLSI

Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents.     

现代电子系统中电源技术的发展和应用

随着电子技术、集成电路和电子产品制作工艺的发展,电源技术不断改革和创新,始终向更清洁、环保、小型、耐用、低能耗等方向发展。本文描述了现代电源的分类、发展、使用和低功耗策略等,并介绍两款低功耗、节能型电源管理芯片,详细说明其特点和使用方法。     

CMOS电路晶体管级功耗优化方法

随着集成电路工艺进入纳米时代,在集成电路设计约束重要性方面,功耗已成为与性能等量齐观的设计约束.由于缺少有效的晶体管级时延模拟器,所以现有的低功耗设计技术均为逻辑门级功耗优化方法.受惠于更低的优化颗粒度,晶体管级优化方法具有比逻辑门级方法更强的静态功耗优化能力,因此针对高静态功耗的纳米工艺芯片,开展晶体管级优化方法的研究具有非常重要的意义.基于晶体管级VLSI模拟器,提出了一种新的晶体管级优化方法用于进一步降低静态功耗,它由两个算法步骤构成:先用聚团策略(clustering)在逻辑门空间来提高优化算法的效率,再用粒度较小的晶体管空间优化算法来提高功耗的优化效果.实验证明所提方法具有以下优点:1) 该方法适用范围较广,可以分析和优化各种电路.这些电路中,每个晶体管都可以有不同的阈值电压V T0、沟道宽度W和沟道长度L.2) 该方法的功耗优化效果较好.在晶体管级W VT0 L的功耗优化实验中,该方法在不降低动态功耗优化效果的前提(动态功耗平均仅增加0.02%)下,在合理的运行时间(优化C7552仅用856.4s)内,在晶体管级对逻辑门级优化结果进行进一步优化,使静态功耗得到进一步降低,平均降低22.85%,最大降低43%.     

Survey of low-power testing of VLSI circuits

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations     

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

With the technology scaling down, low power dissipation has become one of the research focuses in the field of integrated circuit design. Various types of adiabatic logics have been invented for low-power applications. However, the expanding leakage current degrades the performance of conventional adiabatic logics. In this article, a novel improved complementary pass-transistor adiabatic logic （ICPAL） based on fin-type field- effect transistor （FinFET） devices with ultra-low power dissipation has been presented. The proposed ICPAL takes full advantage of different FinFET operating modes, that is, shorted-gate mode, independent-gate mode, and low-power mode, to make a tremendous reduction in power dissipation. For explication and verification, the power dissipation of different ICPAL standard cells has been investigated and compared with other types of adiabatic circuits based on FinFETs. The results show that the ICPAL circuits have ultra-low power dissipation in a wide range of clock frequencies（30-800 MHz） under the condition of similar number of transistors, and the average reduction in power dissipation is about 23.1%, 75.0%, and 50.0% relative to 2N-2N2P, improved pass- transistor adiabatic logic, and complimentary pass-transistor adiabatic logic, respectively. Furthermore, ICPAL supports a better pre-evaluation of system power dissipation in VLSI design and has an intrinsic characteristic for the resistance to some types of side channel attacks.     

CNFET-based approximate ternary adders for energy-efficient image processing applications

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.     

A real-time QoE methodology for AMR codec voice in mobile network

This paper studies a general strategy to predict voice Quality of Experience （QoE） for various mobile networks. Particularly, based on data-mining for Adaptive Multi-Rate （AMR） codec voice, a novel QoE assessment methodology is proposed. The proposed algorithm consists of two parts. The first part is devoted to assessing speech quality of fixed rate codec mode （CM） of AMR while in the other one a adaptive rate CM is designed. Measuring basic network parameters that have much impact on speech quality, QoE can be monitored in rei time for operators. Meanwhile, based on the measurement data sets from real mobile network, the QoE prediction strategy can be implemented and QoE assessment model for AMR codec voice is trained and tested. Finally, the numerical results suggest that the correlation coefficient between predicted values and true values is greater than 90~0 and root mean squared error is less than 0.5 for fixed and adaptive rate CM.     

Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication

Quantum-dot cellular automata (QCA) is an emerging area of research in reversible computing. It can be used to design nanoscale circuits. In nanocommunication, the detection and correction of errors in a received message is a major factor. Besides, device density and power dissipation are the key issues in the nanocommunication architecture. For the first time, QCA-based designs of the reversible low-power odd parity generator and odd parity checker using the Feynman gate have been achieved in this study. Using the proposed parity generator and parity checker circuit, a nanocommunication architecture is proposed. The detection of errors in the received message during transmission is also explored. The proposed QCA Feynman gate outshines the existing ones in terms of area, cell count, and delay. The quantum costs of the proposed conventional reversible circuits and their QCA layouts are calculated and compared, which establishes that the proposed QCA circuits have very low quantum cost compared to conventional designs. The energy dissipation by the layouts is estimated, which ensures the possibility of QCA nano-device serving as an alternative platform for the implementation of reversible circuits. The stability of the proposed circuits under thermal randomness is analyzed, showing the operational efficiency of the circuits. The simulation results of the proposed design are tested with theoretical values, showing the accuracy of the circuits. The proposed circuits can be used to design more complex low-power nanoscale lossless nanocommunication architecture such as nano-transmitters and nano-receivers.     

Power estimation of digital data paths using HEAT

The major concerns of VLSI designers in the past were performance, area, reliability and cost. Power was only a secondary issue. In recent years, however, power, area, and speed have become equally important. There are many reasons for this new trend. Primarily, rapid advancement in semiconductor technology over the past decade has enabled designers to integrate many digital CMOS circuits on a single chip. However, the desirability of using these circuits in portable operations has necessitated the development of low-power technology. Portable applications range from desktop computers and audio-video based multimedia products to personal digital assistants and personal communicators. These systems demand both complex functionality and low power, which make their design challenging. The hierarchical energy analysis tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out     

Modern architecture for photonic networks-on-chip

Development in photonic integrated circuits (PICs) provides a promising solution for on-chip optical computation and communication. PICs provides the best alternative to traditional networks-on-chip (NoC) circuits which face serious challenges such as bandwidth, latency and power consumption. Integrated optics have substantiated the ability to accomplish low-power communication and low-power data processing at ultra-high speeds. In this work, we propose a new architecture for NoC, which might improve overall on-chip network performance by reducing its power consumption, providing large channel capacity for communication, decreasing latency among nodes and reducing hop count. Some of the key features of the proposed architecture are to reduce the waveguide network for communication among nodes, and this architecture can be used as a brick to construct other architectures. In this architecture, we use micro-ring resonator (MRR) and it is used to provide a high bandwidth connection among nodes with a lesser number of waveguide networks. Furthermore, results show that this architecture of PICs provides better performance in terms of low communication latency, low power consumption, high bandwidth. It also provides acceptable FSR value, FWHR value, finesse value and Q-factor of micro-ring resonators used for the design of MRR in this architecture.